適用於短距離通訊系統之0.6伏互補式金氧半導體混合訊號電路設計與實作

Abstract

工業、科學及醫學的領域中，由於對短距離通訊的殷切需求，使得低功率、低成本及高積體化電路的發展得到相當大地關注。為有效減少功率消耗進而延長電池的使用時間，讓積體電路操作於低電壓下將成為未來互補式金氧半導體電路設計的一個新發展方向。然而，因為電晶體運作在弱反轉或是中反轉區，將使轉移電導隨著驅動電壓下降而快速地減少，使得在設計射頻及混合訊號電路上遭遇到嚴苛的限制。因此，本論文將說明實現於標準互補式金氧半導體製程之超低電壓混合訊號電路的設計考量及電路技巧。首先，將介紹適用於超低電壓及低功率應用之頻移鍵控解調器，其使用0.18-μm標準互補式金氧半導體製程。為減輕嚴苛的設計限制，此電路實現於離散時間頻移鍵控之架構下。於電路實現中，為使限制放大器操作於低電壓下，增益單元採用負回授源汲退化之技術。另外，低通濾波器採用Sallen-Key架構，同時考量到功率消耗與晶片大小，因而使用差動差分放大器取代運算放大器之功用。至於關聯器電路中，離散時間微分器實現於延遲單元電路。此解調器操作於0.6伏之供應電壓，消耗功率為2.4mW。接著，將介紹一顆2.4-GHz整數型頻率合成器，其使用0.18-μm標準互補式金氧半導體製程。由於電晶體操作在弱反轉區域中，使得邏輯電路延遲時間隨電壓下降而增加。因此，在除頻器中藉由使用時序重置之技術，可有效減少延遲時間之影響。此頻率合成器操作於0.6伏之供應電壓，消耗功率為7.2mW。最後，利用開關電容電路及脈衝位置調變技術，可以有效降低因為電路之不匹配性及電壓空間不足之問題所產生的突波雜訊。另外，為減少來自電壓與功率之限制而產生效能降低的情況，將針對各元件提出不同的電路架構與設計方法。使用0.18-μm標準互補式金氧半導體製程，2.4-GHz突波抑制頻率合成器操作於0.6伏之供應電壓，消耗功率為7.6mW。

With the strong demands on short-range wireless communications in the industrial, scientific and medical (ISM) band, the evolution of low-power, low-cost and fully integrated electronics systems has attracted great attention. To effectively minimize the power consumption for prolonged battery lifetime, operating the integrated circuits at a reduced supply voltage projects a new development direction for future CMOS designs. However, as the transistors are biased in weak or moderate inversion region, the transconductance decreases drastically with the overdrive voltage, leading to stringent limitations in RF and mixed-signal designs. In this thesis, design considerations and circuit techniques are presented such that ultra-low-voltage operations for mixed-signal integrated circuits can be realized in standard CMOS technologies. Firstly, a frequency shift keying demodulator is presented for ultra-low-voltage and low-power wireless applications. To alleviate the stringent design constraints, the discrete-time frequency shift keying is employed for the realization. In the circuit implementation, negative-feedback source-degeneration gain cells are adopted in the limiting amplifiers for low-voltage operations while the low-pass filters are realized by a Sallen-Key structure with differential difference amplifiers for reduced power consumption and chip area. As for the quadricorrelator, delay cells are utilized in the discrete-time differentiator. Operated at a 0.6-V supply voltage, the fabricated circuit consumes a dc power of 2.4 mW. In the second work, a 2.4-GHz integer-N frequency synthesizer is demonstrated. By using the proposed retiming scheme in the frequency divider, excessive gate delays associated with transistor operations in weak inversion can be effectively decreased, leading to enhanced closed-loop behavior in terms of phase margin and noise shaping. Operated at a reduced supply voltage of 0.6 V, the proposed synthesizer consumes a dc power of 7.2 mW. Finally, by employing the proposed switched-capacitor network and pulse- position-modulation technique, significant reference spurs caused by device mismatch and voltage headroom problems can be effectively suppressed. In addition, various circuit topologies and design strategies are also developed for the individual building blocks such that the performance degradation due to voltage and power limitations can be alleviated. Using a 0.18-μm CMOS process, a 2.4-GHz spur-suppression frequency synthesizer is realized. Operated at a 0.6-V supply, the synthesizer consumes a dc power of 7.6 mW.