低功率雙頻壓控振盪器和5-GHz整數頻率合成器之設計

Abstract

頻率合成器在無線通訊系統裡扮演著重要的角色。在射頻接收器裡，頻率合成器用來作為本地振盪器，將發射或接收的訊號做升頻或降頻的動作。壓控振盪器是頻率合成器裡的一個重要元件，用來產生輸出訊號。本論文分成兩個部分:分別為一個低功率雙頻壓控振盪器和一個5-GHz整數頻率合成器之設計。 為了整合多個標準，我們提出了一個雙頻振盪器，可以同時產生2.4GHz和5GHz的訊號，利用電流再利用的技術，節省功率的消耗。雙頻振盪器的設計使用TSMC 0.18um製程，其消耗功率為3.12 mW、電源為1.2-V。 第二部分，本論文提出了一個5-GHz整數頻率合成器的設計。在此設計中，我們提出一個除二電路，用來降低消耗功率；以及一個電荷幫浦，用以改善傳統架構的線性度。頻率合成器的設計使用TSMC 0.18um製程，其總功率消耗為19.8 mW、電源為1.8-V。當切換頻率為20MHz，鎖定時間為20 us。

A frequency synthesizer plays an important role in a communication system. In RF transceivers, frequency synthesizers are used as local oscillators to up- or down-convert the signal. A voltage-controlled oscillator (VCO) is an essential component of a frequency synthesizer, used to generate the output signal. This Thesis is separated into two parts: a low-power dual-band VCO design and a 5-GHz integer-N frequency synthesizer design. In order to integrate multi-standards, we propose a dual-band VCO (DVCO) which is able to generate 2.4GHz and 5GHz signals simultaneously, and uses current-reuse technique to reduce the power consumption. The core DVCO, designed in TSMC 1P6M 0.18-um process, consumes 3.12mW with a 1.2-V supply. In the second part, the Thesis reports the design of a 5-GHz integer-N frequency synthesizer in TSMC 1P6M 0.18-um process. In this design, a divided-by-2 is proposed to reduce the power consumption, and a charge pump circuit is proposed to improve the linearity. The total power consumption of this synthesizer is 19.8 mW with a 1.8-V supply, and the settling time is 20 us at 20MHz frequency jumping.