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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳少傑(Sao-Jie Chen) | |
| dc.contributor.author | Yun-Chung Chen | en |
| dc.contributor.author | 陳韻中 | zh_TW |
| dc.date.accessioned | 2021-06-15T00:46:30Z | - |
| dc.date.available | 2015-08-19 | |
| dc.date.copyright | 2011-08-19 | |
| dc.date.issued | 2011 | |
| dc.date.submitted | 2011-08-14 | |
| dc.identifier.citation | REFERENCE
[1] IEEE Std 802.11b-1999/Cor 1-2001, “Amendment 2: Higher-Speed Physical Layer (PHY) Extension in the 2.4 GHz band—Corrigendum 1,” in Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, IEEE, New York, 2001. [2] International Standard ISO/IEC 8802-11:1999/Amd 1:2000(E) and IEEE Std 802.11a-1999, “Amendment 1: High-Speed Physical Layer in the 5 GHz Band,” in Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, IEEE, New York, 2000. [3] IEEE Standard 802.11g-2003, “Amendment 4: Further Higher Data Rate Extension in the 2.4 GHz Band,” in Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, IEEE, New York, 2003. [4] B. Razavi, “A Study of Phase Noise in CMOS Oscillators,” IEEE Journal of Solid-State Circuits, Vol. 31, No. 3, pp. 331–343, Mar. 1996. [5] D. B. Leeson, “A Simple Model of Feedback Oscillator Noise Spectrum,” Proceedings of IEEE, Vol. 54, No. 2, pp. 329–330, Feb. 1996. [6] K. Kundert, “Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers,” www.designs-guide.org, 2006. [7] F. Herzel and B. Razavi, “A Study of Oscillator Jitter due to Supply and Substrate Noise,” IEEE Transactions on Circuits and Systems II, Vol. 46, No. 1, pp. 56–62, Jan. 1999. [8] F. M. Gardner, “Charge-Pump Phase-Locked Loops,” IEEE Transactions on Communications, Vol. 28, No. 11, pp. 1849–1858, Nov. 1980. [9] “An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump Phase-Locked Loops,” National Semiconductor Application Note, Jul. 2001. [10] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001. [11] A. Hajimiri and T. H. Lee, “Design Issues in CMOS Differential LC Oscillators,” IEEE Journal of Solid-State Circuits, Vol. 34, No. 5, pp. 717–724, May 1999. [12] S.-M. Yim and K. K. O, “Demonstration of a Switched Resonator Concept in a Dual-Band Monolithic CMOS LC-Tuned VCO,” in Proc. IEEE Custom Integrated Circuits Conference, pp. 205–208, May 2001. [13] C. W. Tang and W. H. Chu, “Integrating a Dual-Band Filter into the Dual-Band VCO Module to Achieve Harmonic Suppression,” Microwave and Optical Technology Letters, Vol. 50, No. 9, pp. 2440–2442, Sep. 2008. [14] H.-L. Kao, D.Y. Yang, C.H. Kao, Y.C. Chang, and B.S. Lin, “Switched Resonators using Adjustable Inductors in 2.4/5 GHz Dual-Band LC VCO,” Electronics Letters, Vol. 44, No. 4, pp. 299–300, Feb. 2008. [15] M. Tiebout, “A CMOS Fully Integrated 1 GHz and 2 GHz Dual-Band VCO with a Voltage Controlled Inductor,” in Proc. European Solid-State Circuits Conference (ESSCIRC), pp. 799–802, Sep. 2002. [16] L. Jia, J. G. Ma, K. S. Yeo, X. P. Yu, M. A. Do, and W. M. Lim, “A 1.8-V 2.4/5.15-GHz Dual-Band LC VCO in 0.18-um CMOS Technology,” IEEE Microwave and Wireless Components Letters, Vol. 16, No. 4, pp. 194–196, Apr. 2006. [17] S. -S. Choi, H. -Y. Yu, and Y. -H. Kim, “A 2.4 /5.2-GHz Dual Band CMOS VCO using Balanced Frequency Doubler with Gate Bias Matching Network,” Journal of Semiconductor Technology and Science, Vol. 9, No. 4, pp. 192–197, Dec. 2009. [18] W.-Z. Chen, J.-X. Chang, Y.-J. Hong, M.-T. Wong, and C.-L. Kuo, “A 2-V 2.3/4.6-GHz Dual-Band Frequency Synthesizer in 0.35-um Digital CMOS Process,” IEEE Journal of Solid-State Circuits, Vol. 39, No. 1, pp. 234–237, Jan. 2004. [19] H. Shin, Z. Xu, and M. F. Chang, “A 1.8-V 6/9-GHz switchable dual-band quadrature LC VCO in SiGe BiCMOS technology,” in Proc. IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 71–74, Jun. 2002. [20] B. Çatlı and M. M. Hella, “A 1.94 to 2.55 GHz, 3.6 to 4.77 GHz Tunable CMOS VCO Based on Double-Tuned, Double-Driven Coupled Resonators,” IEEE Journal of Solid-State Circuits, Vol. 44, No. 9, pp. 2463–2477, Sep. 2009. [21] J. Borremans, A. Bevilacqua, S. Bronckers, M. Dehan, M. Kuijk,P. Wambacq, and J. Craninckx, “A Compact Wideband Front End using a Single Inductor Dual-Band VCO in 90-nm Digital CMOS,” IEEE Journal of Solid-State Circuits, Vol. 43, No. 12, pp. 2693–2705, Dec. 2008. [22] S.-L. Jang, Y.-H. Chuang, C.-C. Chen, S.-H. Lee, and J.-F. Lee, “A CMOS Dual-Band Voltage Controlled Oscillator,” IEEE Asia Pacific Conference, pp. 514–517, Dec. 2006. [23] B. Chang, J. Park, and W. Kim, “A 1.2 GHz CMOS Dual-modulus Prescaler Using New Dynamic D-type Flip-Flop,” IEEE Journal of Solid-State Circuits, Vol. 31, No. 5, pp. 749–752, May 1996. [24] 劉深淵 and 楊清淵, 鎖相迴路, 滄海書局, 2006. [25] P. Larsson, “A 2-1600-MHz CMOS Clock Recovery PLL with Low-Vdd Capability,” IEEE Journal of Solid-State Circuits, Vol. 34, No. 12, pp. 1951–1960, Dec.1999. [26] J. G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-biased Techniques,” IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, pp. 1723–1732, Nov. 1996. [27] B. Razavi, K. F. Lee, and R.-H. Yan, “A 13.4-GHz CMOS frequency divider,” IEEE International Solid-State Circuits Conferenc, pp. 176–177, Feb. 1994. [28] J. M. C. Wong, V. S. L. Cheung, and H. C. Luong, “A 1-V 2.5-mW 5.2-GHz Frequency Divider in a 0.35-um CMOS Process,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 10, pp. 190–193, Oct. 2003. [29] C.-C. Tien, T.-M. Tien, and C. F. Jou, “A 802.11a Pulse-Swallow Integer-N Frequency Synthesizer,” Electromagnetics Research C, Vol. 7, pp. 25–35, 2009. [30] W. Shen, K. Hu, X. Yi, Y. Zhou, and Z. Hong, “A 5GHz CMOS monolithic fractional-N frequency synthesizer,” 6th International Conference on ASIC, Vol. 2, pp. 624–627, Oct. 2005. [31] G. C. T. Leung and H. C. Luong, “1-V 5.2-GHz 27.5-mW fully-integrated CMOS WLAN synthesizer,” European Solid-State Circuits Conference (ESSCIRC), pp. 103–106, Sep. 2003. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/42097 | - |
| dc.description.abstract | 頻率合成器在無線通訊系統裡扮演著重要的角色。在射頻接收器裡，頻率合成器用來作為本地振盪器，將發射或接收的訊號做升頻或降頻的動作。壓控振盪器是頻率合成器裡的一個重要元件，用來產生輸出訊號。本論文分成兩個部分:分別為一個低功率雙頻壓控振盪器和一個5-GHz整數頻率合成器之設計。
為了整合多個標準，我們提出了一個雙頻振盪器，可以同時產生2.4GHz和5GHz的訊號，利用電流再利用的技術，節省功率的消耗。雙頻振盪器的設計使用TSMC 0.18um製程，其消耗功率為3.12 mW、電源為1.2-V。 第二部分，本論文提出了一個5-GHz整數頻率合成器的設計。在此設計中，我們提出一個除二電路，用來降低消耗功率；以及一個電荷幫浦，用以改善傳統架構的線性度。頻率合成器的設計使用TSMC 0.18um製程，其總功率消耗為19.8 mW、電源為1.8-V。當切換頻率為20MHz，鎖定時間為20 us。 | zh_TW |
| dc.description.abstract | A frequency synthesizer plays an important role in a communication system. In RF transceivers, frequency synthesizers are used as local oscillators to up- or down-convert the signal. A voltage-controlled oscillator (VCO) is an essential component of a frequency synthesizer, used to generate the output signal. This Thesis is separated into two parts: a low-power dual-band VCO design and a 5-GHz integer-N frequency synthesizer design.
In order to integrate multi-standards, we propose a dual-band VCO (DVCO) which is able to generate 2.4GHz and 5GHz signals simultaneously, and uses current-reuse technique to reduce the power consumption. The core DVCO, designed in TSMC 1P6M 0.18-um process, consumes 3.12mW with a 1.2-V supply. In the second part, the Thesis reports the design of a 5-GHz integer-N frequency synthesizer in TSMC 1P6M 0.18-um process. In this design, a divided-by-2 is proposed to reduce the power consumption, and a charge pump circuit is proposed to improve the linearity. The total power consumption of this synthesizer is 19.8 mW with a 1.8-V supply, and the settling time is 20 us at 20MHz frequency jumping. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T00:46:30Z (GMT). No. of bitstreams: 1 ntu-100-R98943128-1.pdf: 2435418 bytes, checksum: 8d84dd71a808f75ded6e71232f8c18d4 (MD5) Previous issue date: 2011 | en |
| dc.description.tableofcontents | TABLE OF CONTENTS
ABSTRACT i LIST OF FIGURES v LIST OF TABLE ix CHAPTER 1 INTRODUCTION 1 1.1 Motivation 1 1.2 IEEE 802.11a/b/g 1 1.3 Contributions of this Thesis 3 1.4 Thesis Organization 4 CHAPTER 2 BASICS OF PLL-BASED FREQUENCY SYNTHSIZER 5 2.1 PLL Basics 5 2.2 Building Blocks in PLLs 6 2.2.1 Phase-Frequency Detector and Charge Pump 6 2.2.2 Loop Filter 10 2.2.3 Divider 11 2.2.4 Voltage-Controlled Oscillator 12 2.3 Non-ideal Effect in PLLs 13 2.3.1 Phase Noise 13 2.3.2 Jitter 16 2.3.3 Spurs 19 2.4 Architectures of Frequency Synthesizers 20 CHAPTER 3 PLL ANALYSIS 23 3.1 Linear Transfer Function 23 3.2 Charge-Pump PLL Design 24 3.2.1 Second-Order PLL 24 3.2.2 Third-Order PLL 26 3.2.3 Fourth-Order PLL 29 3.2.4 Settling Time 31 3.3 Phase Noise Analysis 32 CHAPTER 4 LOW POWER DUAL-BAND VCO 37 4.1 Introduction 37 4.2 Basic LC Oscillator Topologies 38 4.3 Dual-Band VCOs 43 4.3.1 Architectures of Dual-Band Frequency Synthesizers 43 4.3.2 Related Works 44 4.3.3 Proposed DVCO 46 4.3.4 Circuit Implementation 49 4.3.5 Experimental Results 54 4.4 Summary 57 CHAPTER 5 5-GHz INTEGER-N FREQUENCY SYNTHESIZER 61 5.1 Circuit Implementation 61 5.1.1 Divided-by-Two Circuit 62 5.1.2 Multi-Modulus Divider 66 5.1.3 Charge Pump 68 5.1.4 Phase-Frequency Detector 71 5.1.5 Voltage-Controlled Oscillator 72 5.2 Simulation Results 73 5.2.1 Behavior System Simulation Results 73 5.2.2 Transistor-Level Simulation Results 74 5.3 Summary 79 CHAPTER 6 CONCLUSION 83 REFERENCE 85 | |
| dc.language.iso | en | |
| dc.subject | 電荷幫浦 | zh_TW |
| dc.subject | 壓控振盪器 | zh_TW |
| dc.subject | 雙頻 | zh_TW |
| dc.subject | 頻率合成器 | zh_TW |
| dc.subject | 除二電路 | zh_TW |
| dc.subject | Frequency Synthesizer | en |
| dc.subject | Charge Pump | en |
| dc.subject | divided-by-2 | en |
| dc.subject | VCO | en |
| dc.subject | Dual-Band | en |
| dc.title | 低功率雙頻壓控振盪器和5-GHz整數頻率合成器之設計 | zh_TW |
| dc.title | Design of a Low-Power Dual-Band VCO and a 5-GHz Integer-N Frequency Synthesizer | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 99-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 盧信嘉(Hsin-Chia Lu),林宗賢(Tsung-Hsien Lin),曹恆偉(Hen-Wai Tsao) | |
| dc.subject.keyword | 壓控振盪器,雙頻,頻率合成器,除二電路,電荷幫浦, | zh_TW |
| dc.subject.keyword | VCO,Dual-Band,Frequency Synthesizer,divided-by-2,Charge Pump, | en |
| dc.relation.page | 88 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2011-08-15 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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