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標題: | 近電晶體截止頻率之金氧半導體毫米波積體電路設計與實作 Design and Implementation of CMOS Millimeter-Wave Integrated Circuits near the Transistor Cutoff Frequency |
作者: | Hsieh-Hung Hsieh 謝協宏 |
指導教授: | 呂良鴻 |
關鍵字: | 互補式金氧半導體,毫米波,低雜訊放大器,壓控振盪器,注入式鎖定除頻器, CMOS,millimeter wave,low-noise amplifier,voltage-controlled oscillator,injection-locked frequency divider, |
出版年 : | 2008 |
學位: | 博士 |
摘要: | 近年來,隨著互補式金氧半導體技術日趨成熟,深次微米製程的電晶體截止頻率及最大振盪頻率已超過100 GHz,因而使射頻積體電路得以朝高頻發展。然而,目前金氧半導體毫米波電路的特性,依然受制於許多製程上先天的缺陷,例如:寄生效應、基板損耗及不足的元件能力。因此,近電晶體截止頻率的金氧半導體電路設計,仍是一深具挑戰的研究課題。
本篇論文,為克服互補式金氧半導體頻率限制,提出了一系列創新的電路架構。在第三章中,藉由使用增益放大的技巧,可使高頻低雜訊放大器的小信號增益獲得改善。在第四章中,基於導納轉換的概念,傳統的電感電容共振腔壓控振盪器將可操作於近電晶體截止頻率範圍。在第五章中,透過採用串聯電感補償技術,除四頻率除頻器的鎖定頻寬能有效增大;不僅如此,由於所提出的除四除頻器,無須串接兩級除二電路,故可降低佈局面積,並減少直流功率的消耗。 Due to recent advances in the fabrication technology, transistors with a cutoff frequency (fT) and a maximum oscillation frequency (fmax) beyond 100 GHz have been commercially available in a deep-submicron CMOS process, motivating RF integrated circuit designs towards higher frequencies. Unfortunately, the development of CMOS millimeter-wave circuits has been long impeded by inherent shortcomings such as parasitic components, substrate losses and inferior device capabilities. It is still a challenging task for the designer to realize CMOS circuits near the transistor cutoff frequency. In this thesis, to alleviate the frequency limitations imposed on CMOS technologies, novel circuit topologies are developed for millimeter-wave operations. In Chapter 3, a gain-enhancement technique is introduced to the low-noise amplifier (LNA) while the small-signal gain is boosted, facilitating circuit operations at higher frequency bands. In Chapter 4, based on the concept of the admittance transformation, the proposed LC-tank voltage-controlled oscillator (VCO) is capable of sustaining the fundamental oscillation at a frequency close to the fT of the transistor. In Chapter 5, by adopting a series-peaking structure, the locking range of the harmonic injection-locked frequency divider is effectively enhanced while the compact integration and reduced dc power can be exhibited since the cascaded divide-by-two stages are avoided. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/41849 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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