使用多重擷取時脈高速掃描測試圖樣的轉換錯誤診斷

Abstract

本論文提出一個電路診斷技術，可以使用多擷取時脈的高速掃描測試圖樣，定位電路中的轉換錯誤。為了快速的找出錯誤可能發生的地方，本論文提出了兩層的搜尋方法。首先，電路將被分成許多的無扇出區域，許多的無扇出區域再被分組成許多的無扇出區域群。此技術使用“X”作為錯誤影響的模型，所以錯誤的大小不會影響診斷的結果。使用Intel 64位元2.0GHz的CPU的機器，對ISCAS’89基準電路所做的實驗顯示，平均而言，使用六個擷取時脈的測試圖樣，所有的轉換電路可以在21秒內被準確的診斷出來。本論文所提出的技術非常適合使用在診斷短延遲錯誤，這是使用單一擷取時脈的慢速掃描測試圖樣所無法診斷出的。

This thesis presents a diagnosis technique to locate transition faults using scan patterns with multiple capture clocks which are applied at speed. To quickly locate the candidate faults, a two-level search is proposed. The circuit is first partitioned into fanout-free regions (FFR’s), which are then partitioned into FFR groups. This technique uses the unknown “X” to model the fault effect so the fault size does not affect the diagnosis results. Experiments on ISCAS’89 large benchmark circuits with Intel 64-bit 2.0 GHz CPU show that, on the average, all transition faults are accurately diagnosed in 21 seconds using test patterns of six capture clocks. The proposed technique is suitable for small delay defects that cannot be diagnosed using slow speed scan test patterns with a single capture clock.