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| ???org.dspace.app.webui.jsptag.ItemTag.dcfield??? | Value | Language |
|---|---|---|
| dc.contributor.advisor | 李建模(Chien-Mo Li) | |
| dc.contributor.author | Shang-Feng Chao | en |
| dc.contributor.author | 趙上鋒 | zh_TW |
| dc.date.accessioned | 2021-06-14T16:53:41Z | - |
| dc.date.available | 2011-08-05 | |
| dc.date.copyright | 2008-08-05 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-07-29 | |
| dc.identifier.citation | [Abramovici 82] M. Abramovici and M. A. Breuer, “Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect-Cause Analysis,” IEEE Transactions on Computers, Vol. 31, No. 12, pp. 1165-1172, 1982.
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Cheng, “Transition Fault Simulation for Sequential Circuits,” Proceedings of IEEE International Test Conference, pp. 723-731, 1992. [Cheng 93] K. T. Cheng, “Transition fault testing for sequential circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, NO.12, pp.1971-1983, 1993. [Chen 03] G. Chen, S. M. Reddy, I. Pomeranz, “Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits,” Proceedings of IEEE International Conference on Computer Design, 2003. [Cox 88] H. Cox and J. Rajski, “A Method of Fault Analysis for Test Generation and Fault Diagnosis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 7, No. 7, pp. 813-833, July 1988. [D’Souza 95] A. D’Souza and M. Hsiao, “Error Diagnosis of Sequential Circuits Using Region-Based Model,” Journal of Electronic Testing Theory and Application, Vol. 21, pp. 115-126, 2005. [Dastidar 98] J. G. Dastidar and N. Touba, “A systematic Approach for Diagnosing Multiple Delay Faults,” Proceedings of IEEE International Symposium Defect and Fault-Tolerance in VLSI Systems, pp. 211-216, 1998. [Girard 92] P. Girard, C. Landrault, and S. Pravossoudovitch, “Delay-Fault Diagnosis by Critical Path Tracing,” IEEE Design & Test of Computers, Vol. 9, No. 4, pp. 27-32, 1992. [Hsu 98] Y. C. Hsu and S. K. Gupta, “A New Path-Oriented Effect-Cause Methodology to Diagnose Delay failures,” Proceedings of IEEE International Test Conference, pp. 758-767, 1998. [Huang 97] S. Y. Huang, K. T. Cheng, K. C. Chen, and D. I. Cheng, “ErrorTracer: A Fault Simulation-Based Approach to Design Error Diagnosis,” Proceedings of IEEE International Test Conference, pp. 974-981, 1997. [Huisman 05] L. M. Huisman, Data mining and Diagnosis of IC Fail, Springer, 2005. [ITRS 06] Semiconductor Industry Association. (2006). International Technology Roadmap for Semiconductors 2006 Update – Test and Test Equipment. http://www.itrs.net/Links/2006Update/FinalToPost/03_Test2006Update.pdf [Kim 03] K. S. Kim, S. Mitra, and P. Ryan, “Delay Defect Characteristics and Testing Strategies,” IEEE Design & Test of Computers, Vol. 20, No. 5, pp. 8- 16, 2003. [Kuo 92] S. Y. Kuo, “Locating Logic Design Errors via Test Generation and Don’t Care Propagation,” Proceedings of IEEE European Design and Test Conference, pp. 466-471, 1992. [Lee 96] H. K. Lee and D. S. Ha, “HOPE: an Efficient Parallel Fault Simulator for Synchronous Sequential Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 9, pp. 1048-1058, Sep. 1996. [Lu 07] S. Y. Lu, M. T. Hsieh, and J. J. Liou, “An Efficient SAT-based Path Delay Fault ATPG with an Unified Sensitization Model,” Proceedings of IEEE International Test Conference, 2007. [Niemann 92] T. M. Niemann, W. T. Cheng, and J. H. Patel, “PROOFS: A Fast, Memory-efficient Sequential Circuit Fault Simulator,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 11, No. 2., pp198-207, Feb. 1992. [Nigh 00] P. Nigh and A. Gattiker, “Test Method Evaluation Experiments and Data,” Proceedings of IEEE International Test Conference, pp. 454-463, 2000. [Pant 99] P. Pant and A. Chatterjee, “Efficient Diagnosis of Path Delay Faults in Digital Logic Circuits,” Proceedings of IEEE International Conference on Computer-Aided Design, pp. 471-476, 1999. [Pomeranz 91] I. Pomeranz and S. Reddy, “On Achieving a Complete Fault Coverage for Sequential Machines Using the Transition Fault Model,” Proceedings of IEEE/ACM Design Automation Conference, pp. 341-346, 1991. [Poku 07] O. Poku and S. Blanton, “Delay Defect Diagnosis Using Segment Network Faults,” Proceedings of IEEE International Test Conference, 2007. [Tseng 01] C. W. Tseng and E. J. McCluskey, “Multiple-output Propagation Transition Fault Test,” Proceedings of IEEE International Test Conference, pp. 358-366, 2001. [Venkataraman 01] S. Venkataraman and S. B. Drummonds, “Poirot: Applications of a Logic Fault Diagnosis Tool,” IEEE Design & Test of Computers, Vol. 18, No. 1, pp. 19-30, 2001. [Waicukauski 87] J. Waicukauski and et. al. “Transition Fault Simulation,” IEEE Design & Test of Computers, Vol. 4, No. 2, pp. 32-38, 1987. [Wang 06] L. T. Wang, C. W. Wu, and X. Wen, VLSI Test Principles and Architectures: Design for Testability, Elsevier Science, July 2006. [Yen 08] Chia-Chih Yen and et. al., “A General Failure Candidate Ranking Framework for Silicon Debug,” Proceedings of IEEE VLSI Test Symposium, pp. 352-358, 2008 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/40624 | - |
| dc.description.abstract | 本論文提出一個電路診斷技術，可以使用多擷取時脈的高速掃描測試圖樣，定位電路中的轉換錯誤。為了快速的找出錯誤可能發生的地方，本論文提出了兩層的搜尋方法。首先，電路將被分成許多的無扇出區域，許多的無扇出區域再被分組成許多的無扇出區域群。此技術使用“X”作為錯誤影響的模型，所以錯誤的大小不會影響診斷的結果。使用Intel 64位元2.0GHz的CPU的機器，對ISCAS’89基準電路所做的實驗顯示，平均而言，使用六個擷取時脈的測試圖樣，所有的轉換電路可以在21秒內被準確的診斷出來。本論文所提出的技術非常適合使用在診斷短延遲錯誤，這是使用單一擷取時脈的慢速掃描測試圖樣所無法診斷出的。 | zh_TW |
| dc.description.abstract | This thesis presents a diagnosis technique to locate transition faults using scan patterns with multiple capture clocks which are applied at speed. To quickly locate the candidate faults, a two-level search is proposed. The circuit is first partitioned into fanout-free regions (FFR’s), which are then partitioned into FFR groups. This technique uses the unknown “X” to model the fault effect so the fault size does not affect the diagnosis results. Experiments on ISCAS’89 large benchmark circuits with Intel 64-bit 2.0 GHz CPU show that, on the average, all transition faults are accurately diagnosed in 21 seconds using test patterns of six capture clocks. The proposed technique is suitable for small delay defects that cannot be diagnosed using slow speed scan test patterns with a single capture clock. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-14T16:53:41Z (GMT). No. of bitstreams: 1 ntu-97-R95943084-1.pdf: 1315032 bytes, checksum: 75c50547b94bb0df81f031ac377cbc78 (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | 摘要 i
Abstract ii Table of Contents iii List of Figures v List of Tables vii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Proposed Technique and Contribution 3 1.3 Organization 4 Chapter 2 Background 5 2.1 Sequential Fault Simulation 5 2.1.1 Differential Fault Simulation 6 2.1.2 Proofs 7 2.1.3 Hope 10 2.2 Sequential Diagnosis 16 2.3 X Fault Model 16 Chapter 3 Proposed Diagnosis Technique 19 3.1 Overall Diagnosis Flow 19 3.2 Preprocessor 20 3.3 Group Mode FFR Finder 23 3.4 Single Mode FFR Finder 29 3.5 Fault Simulator 34 3.6 Complexity Analysis 38 Chapter 4 Experimental Results 39 4.1 Diagnosis Results of Each Phase 42 4.2 Different Sequential Depths 46 4.3 Random Fault Sizes 47 4.4 Slow-to-rise/fall faults 48 Chapter 5 Discussion 49 5.1 Design Error Debugging 49 5.2 Other fault models 49 5.3 Comparison with Critical Path Tracing 50 5.4 Diagnosis with Functional Pattern 52 5.5 Backward Implication 53 Chapter 6 Summary 54 Reference 55 | |
| dc.language.iso | zh-TW | |
| dc.title | 使用多重擷取時脈高速掃描測試圖樣的轉換錯誤診斷 | zh_TW |
| dc.title | Transition Fault Diagnosis Using At-Speed Scan Patterns with Multiple Capture Clocks | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 96-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 饒建奇(Jiann-Chyi Rau),黃鐘揚(Chung-Yang Huang) | |
| dc.subject.keyword | 轉換錯誤,診斷,多擷取時脈,無扇出區域, | zh_TW |
| dc.subject.keyword | transition fault,diagnosis,at-speed,multiple capture clocks,fanout-free region, | en |
| dc.relation.page | 57 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2008-07-30 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| Appears in Collections: | 電子工程學研究所 | |
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| File | Size | Format | |
|---|---|---|---|
| ntu-97-1.pdf Restricted Access | 1.28 MB | Adobe PDF |
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