三維晶片中同時切換雜訊最小化的直通矽晶連通柱擺置設計

Abstract

隨著高速數位電路的設計趨勢朝向高操作頻率、高功率密度、低電壓位準和更微小的尺寸，維持電路系統的訊號完整度和電源完整度成為設計上的一大挑戰，而同時切換雜訊或稱為接地反彈雜訊的產生造成電源品質的不穩定，影響了電路運作的可靠性。 本論文使用基因演算法獲得在三維晶片中最佳的直通矽晶連通柱陣列擺置方式，以降低同時切換雜訊的影響。使用等效阻抗矩陣法求得晶片內部複雜構裝的等效電感矩陣，並使用等效電流源取代完整輸入輸出緩衝器模型，以建立一套快速計算接地反彈雜訊峰值的程式。利用基因演算法的尋優機制，將訊號/接地或訊號/接地/電源的直通矽晶連通柱陣列擺置方式最佳化。再者，可以在各種尺寸或訊號/接地/電源的比例下，得到適當的擺置方式將同時切換雜訊最小化。

Toward the design trends of high clock frequencies, high power density, low voltage levels, and small size for high-speed digital systems, the simultaneous switching noise (SSN) or ground bounce noise (GBN) in the circuits is becoming one of the major challenges for signal integrity (SI) and power integrity (PI). This paper presents a design methodology to obtain the signal-ground or signal-ground-power through-silicon via (TSV) patterns in the on-chip power delivery network (PDN) with the minimized SSN using a genetic algorithm (GA). For the complex on-chip PDN, the equivalent impedance matrix method is used to calculate the equivalent inductance matrix for desired TSV patterns. The fast computational program to achieve the peak SSN analysis is developed with the simplified I/O buffer model. Based on the proposed methodology, the GA optimization for proper TSV pattern assignments with the various size and signal/ground/power ratios are shown and discussed.