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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳瑞北(Reuy-Beei Wu) | |
| dc.contributor.author | Hsiang-Yuan Cheng | en |
| dc.contributor.author | 鄭翔元 | zh_TW |
| dc.date.accessioned | 2021-06-13T17:31:18Z | - |
| dc.date.available | 2011-08-23 | |
| dc.date.copyright | 2011-08-23 | |
| dc.date.issued | 2011 | |
| dc.date.submitted | 2011-08-19 | |
| dc.identifier.citation | [1] M. Swaminathan and A. E. Engin, Power Integrity Modeling and Design for Semiconductors and Systems. Upper Saddle River, New Jerrsey, USA: Pearson Education, 2008, Chapter 3.
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Symp., June 22-27, 2003, Columbus, Ohio, USA, vol. 2, pp. 884–887. [35] A.-S. Liu, R.-B. Wu, Y.-C. Lin, and H.-J. Li, “Synthesis of nonuniformly spaced linear array for GSM/DCS/WCDMA base atation application using genetic algorithm”, in IEEE Antennas Propag. Symp., June 20-25, 2004, Monterey, California, USA, vol. 1, pp. 137–140. [36] A.-S. Liu, R.-B. Wu, and Y.-C. Yu, “A two-phase full-wave GA optimization for W-band image rejection waveguide filter design,” in IEEE Antennas Propag. Symp., June 22-27, 2003, Columbus, Ohio, USA, vol. 2, pp. 60–63. [37] C.-H. Chien, A.-S. Liu, and R.-B. Wu, “A functional genome optimization method for CPW filters design,” in IEEE Antennas Propag. Symp., June 20-25, 2004, Monterey, California, USA, vol. 3, pp. 2743—2746. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/39542 | - |
| dc.description.abstract | 隨著高速數位電路的設計趨勢朝向高操作頻率、高功率密度、低電壓位準和更微小的尺寸，維持電路系統的訊號完整度和電源完整度成為設計上的一大挑戰，而同時切換雜訊或稱為接地反彈雜訊的產生造成電源品質的不穩定，影響了電路運作的可靠性。
本論文使用基因演算法獲得在三維晶片中最佳的直通矽晶連通柱陣列擺置方式，以降低同時切換雜訊的影響。使用等效阻抗矩陣法求得晶片內部複雜構裝的等效電感矩陣，並使用等效電流源取代完整輸入輸出緩衝器模型，以建立一套快速計算接地反彈雜訊峰值的程式。利用基因演算法的尋優機制，將訊號/接地或訊號/接地/電源的直通矽晶連通柱陣列擺置方式最佳化。再者，可以在各種尺寸或訊號/接地/電源的比例下，得到適當的擺置方式將同時切換雜訊最小化。 | zh_TW |
| dc.description.abstract | Toward the design trends of high clock frequencies, high power density, low voltage levels, and small size for high-speed digital systems, the simultaneous switching noise (SSN) or ground bounce noise (GBN) in the circuits is becoming one of the major challenges for signal integrity (SI) and power integrity (PI).
This paper presents a design methodology to obtain the signal-ground or signal-ground-power through-silicon via (TSV) patterns in the on-chip power delivery network (PDN) with the minimized SSN using a genetic algorithm (GA). For the complex on-chip PDN, the equivalent impedance matrix method is used to calculate the equivalent inductance matrix for desired TSV patterns. The fast computational program to achieve the peak SSN analysis is developed with the simplified I/O buffer model. Based on the proposed methodology, the GA optimization for proper TSV pattern assignments with the various size and signal/ground/power ratios are shown and discussed. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T17:31:18Z (GMT). No. of bitstreams: 1 ntu-100-R98942086-1.pdf: 2377512 bytes, checksum: 5b6f58d919cb7f6d92d701ca40467ccf (MD5) Previous issue date: 2011 | en |
| dc.description.tableofcontents | 摘 要… I
Abstract II 目 錄… III 圖 例… VI 表 格… IX 第一章 緒論 1 1-1 研究動機與目的 1 1-2 文獻回顧與探討 2 1-3 章節概要 5 1-4 貢獻 6 第二章 三維晶片電源網路的同時切換雜訊計算 8 2-1 同時切換雜訊的機制 8 2-2 電感基本理論 10 2-3 三維晶片電源傳輸網路介紹 12 2-4 輸入輸出緩衝器的等效模型建立 14 2-5 電源傳輸網格和直通矽晶連通柱的等效模型建立 22 2-5-1 電源傳輸網格的等效模型建立 23 2-5-2 直通矽晶連通柱陣列的等效模型建立 25 2-5-3 將電源傳輸網格與直通矽晶連通柱陣列的電感矩陣結合 25 2-6 輸入輸出緩衝器簡化模型的驗證 26 第三章 以等效阻抗矩陣法計算電感矩陣並估算雜訊峰值 29 3-1 等效阻抗矩陣法介紹 31 3-2 等效阻抗矩陣法計算訊號/接地擺置的同時切換雜訊 33 3-3 當電源網格尺寸改變的接地/訊號同時切換雜訊估算 37 3-4 訊號/電源/接地擺置的同時切換雜訊估算 42 第四章 使用基因演算法對直通矽晶連通柱陣列擺置方式最佳化 49 4-1 基因演算法簡介 49 4-2 基因演算法基本術語 50 4-3 以基因演算法對訊號/接地擺置方式最佳化 51 4-3-1 訊號/接地擺置方式最佳化流程說明 51 4-3-2 訊號/接地擺置方式最佳化結果 57 4-4 以基因演算法對訊號/接地/電源擺置方式最佳化 62 4-4-1 訊號/接地/電源擺置方式之最佳化流程說明 62 4-4-2 訊號/接地/電源擺置方式最佳化結果 63 第五章 結論與未來工作 69 5-1 結論 69 5-2 未來工作 70 參考文獻 71 | |
| dc.language.iso | zh-TW | |
| dc.subject | 直通矽晶連通柱 | zh_TW |
| dc.subject | 同時切換雜訊 | zh_TW |
| dc.subject | 基因演算法 | zh_TW |
| dc.subject | Genetic algorithm (GA) | en |
| dc.subject | simultaneous switching noise (SSN) | en |
| dc.subject | through-silicon via (TSV) | en |
| dc.title | 三維晶片中同時切換雜訊最小化的直通矽晶連通柱擺置設計 | zh_TW |
| dc.title | Design of Through Silicon Via Assignments for Minimizing Simultaneous Switching Noise in 3D IC | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 99-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 吳宗霖(Tzong-Lin Wu),林建民(Chien-Min Lin),駱韋仲(Wei-Chung Luo) | |
| dc.subject.keyword | 直通矽晶連通柱,同時切換雜訊,基因演算法, | zh_TW |
| dc.subject.keyword | Genetic algorithm (GA),simultaneous switching noise (SSN),through-silicon via (TSV), | en |
| dc.relation.page | 72 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2011-08-20 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
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