覆晶式設計中繞線系統之研發

Abstract

覆晶式(flip-chip)封裝(package)提供了最高密度的封裝方式，用來支援受 接合點(pad)限制的特殊應用積體電路(ASIC)設計。在此論文中，我們提供了第 一個應用於覆晶式封裝的繞線器(router)。此繞線器能將打線接合點(wirebonding pads)重新分配到凸塊接合點(bump pads)上然後完成每一個接合點的繞 線。先執行全域繞線(global routing)再執行細部繞線(detailed routing)的兩 階段技術是此繞線器的核心概念。在全域繞線中，我們使用了網路流演算法 (network flow algorithm)來解決將打線接合點重新分配到凸塊接合點上的問題 並且產生每一條訊號線的全域繞線路徑。在細部繞線中，我們使用了三個方法來 逐步完成細部繞線。這三個方法分別是越過點分派法(cross point assignment)、繞線順序決定法(net ordering determination)和軌道分派法 (track assignment)。在實驗方面，我們使用了七個來自工業界的測試檔案來證 明我們的繞線器演算法比工業界的繞線器演算法在總線長(total wirelength) 減少了10.2%、關鍵線長(critical wirelenght)減少了13.4%而在訊號歪斜 (signal skew)更是減少了13.9%。

The flip-chip package gives the highest chip density of any packaging method to support the pad-limited Application-Specific Integrated Circuit (ASIC) designs. In this thesis, we propose the first router for the flip-chip package. The router can redistribute nets from wire-bonding pads to bump pads and then route each of them. The router adopts a two-stage technique of global routing followed by detailed routing. In global routing, we use the network flow algorithm to solve the assignment problem from the wire-bonding pads to the bump pads, and then create the global routing path for each net. The detailed routing consists of three stages, cross point assignment, net ordering determination, and track assignment, to complete the routing. Experimental results based on seven real designs from the industry demonstrate that the router can reduce the total wirelength by 10.2%, the critical wirelength by 13.4%, and the signal skews by 13.9%, compared with a heuristic algorithm currently used in industry.