應用於被動光纖網路之突發式時脈資料回復電路

Abstract

這篇論文的內容在於，應用於被動光纖網路之突發式時脈資料回復電路的動機、挑戰、和方法。 先介紹為何需要資料時脈回復電路。再來則是對於被動光纖網路的解說，從而了解為何需要突發式的資料時脈回復電路。第一章的重點在於動機，除了動機之外，與突發式資料時脈回復電路相關之被動式光纖網路的規格，也將在這一章當中介紹。 將現有文獻的突發式資料時脈回復電路分為三大類後，分別解說其運作方式。在了解這些基本架構之後，以可達到的傳輸率、鎖定時間、功率、面積、和時間抖動的特性去比較這三大類的優缺點。經過比較之後，將更能清楚地定義出問題，進而提出可行的解決方法。所以，在接下來部分，將介紹兩個所提出的2.5Gbps突發式時脈資料回復電路。 第一個作品為一利用過取樣(Oversampling)的數位形式突發式資料時脈回復電路，其主要是改良自[13]。但我們利用了不同於[13]的演算法，縮短其主要限制操作速度的路徑，而得到更高的傳輸率(2.5Gbps)與低功率消耗(資料時脈回復電路部份33mW)的效果。這一次實作是以0.18微米的標準互補式金氧半製程實現，總面積為1.5mm x 1.01mm。 第二個作品則是利用除頻器產生多頻帶接收能力之突發式時脈資料回復電路。不同於前者的方式，這次所使用的架構並非過取樣，而是利用閘式壓控振盪器(Gated Voltage-Controlled Oscillator)來達到。閘式壓控振盪器即為一可被停止的壓控振盪器，因為其由邏輯閘電路所組成。所以我們將對壓控振盪器作分析，以了解在提高傳輸率至2.5Gbps的同時，將會遭遇到什麼問題，並在之後介紹所提出的閘式壓控振盪器。利用所提出之閘式壓控震盪器和修改過後的除頻器，此電路可接收2488.32Mbps, 1244.16Mbps, 622.08Mbps,及155.52Mbps速率之資料，總功率消耗為70mW。在此次實驗當中，也對Jitter Tolerance作了量測，故在其後對此特性作了分析。此作也是以0.18微米的標準互補式金氧半製程實現，總面積為1.48mm x 0.92mm。

In this thesis, the motivation, challenges, and solutions of burst-mode clock and data recovery (BMCDR) circuits for passive optical networks (PONs) are presented. The need for clock and data recovery circuits is explained first. Then, the basic architecture of a PON is analyzed so that the BMCDR circuits can be realized. The motivation and the specifications related to BMCDR circuits are also introduced. The existing BMCDR circuits are classified into three categories in this thesis. After introducing every category, a comparison in view of achievable data rate, locking time, power, area, and jitter performance is made. Summarizing the comparisons, the challenges manifest clearly. Thus, two 2.5Gbps BMCDR circuits are presented. Chapter 3 and chapter 4 give the details of these two circuits. A digital-type BMCDR circuit using oversampling is presented. It is modified from [13]. However, with the modified algorithm, the critical path is shortened. A higher-speed (2.5Gbps) and low-power (33mW) BMCDR circuit is obtained. It is implemented in a standard 0.18um CMOS process and the area is 1.5mm x 1.01mm. Besides the former circuit, a multi-band BMCDR circuit using frequency dividers is implemented. Instead of oversampling, this work is based on gated voltage-controlled-oscillator (GVCO) that is namely a stoppable VCO because it is composed of logic gates. Before the proposed GVCO, the analysis of VCO is made to understand the problem encountered when designing a 2.5Gbps GVCO-based BMCDR circuit. With the proposed GVCO and modified frequency dividers, multi-band operation (2488.32Mbps, 1244.16Mbps, 622.08Mbps, and 155.52Mbps) is achieved while consuming 70mW. In addition, the jitter tolerance of this burst-mode CDR circuit is also measured and analyzed. The chip is also implemented in a standard 0.18um CMOS process and the area is 1.48mm x 0.92mm.