請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/38248完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉深淵 | |
| dc.contributor.author | Sy-Chyuan Hwu | en |
| dc.contributor.author | 胡思全 | zh_TW |
| dc.date.accessioned | 2021-06-13T16:28:45Z | - |
| dc.date.available | 2007-07-22 | |
| dc.date.copyright | 2005-07-22 | |
| dc.date.issued | 2005 | |
| dc.date.submitted | 2005-07-13 | |
| dc.identifier.citation | [1] J. Scheytt, G. Hanke and U. Langmann, “A 0.155, 0.622 and 2.488Gb/s
automatic bit-rate selecting clock and data recovery IC for bit-rate transparent SDH systems,” IEEE Journal of Solid-State Circuits, sc-34, pp. 1935-1943, Dec. 1999. [2] G. Kramer and G. Pesavento, Alloptic, Inc., “Ethernet Passive Optical Network (EPON): Building a Next-Generation Optical Access Network,” IEEE Communications Magazine, Topics in LIGHTWAVE, pp. 66-73, Feb. 2002. [3] S. Yamashita, S. Ide, K. Mori, A. Hayakawa, N. Ueno, and K. Tanaka, “Novel Cell-AGC Technique for Burst-Mode CMOS Preamplifier With Wide Dynamic Range and High Sensitivity for ATM-PON System,” IEEE Journal of Solid-State Circuits, vol. 37, no. 7, pp. 881-886, July 2002. [4] “G.984.2 Gigabit-capable passive optical networks (GPON): Physical media dependent (PMD) layer,” ITU-T, 2003. [5] IEEE 802.3ah Draft Standard, July 2003. [6] Q. Le, S. Lee, Y. Oh, H. Kang, and T. Yoo, “A Burst-Mode Receiver for 1.25-Gb/s Ethernet PON With AGC and Internally Created Reset Signal,” IEEE Journal of Solid-State Circuits, vol. 39, no. 12, pp. 2379-2388, Dec. 2004. [7] P. Han, C. Lee, and W. Choi, “A novel 622Mbps burst mode CDR circuit using two-loop switching,” Journal of Semiconductor Technology and Science, vol.3, no.4, pp.188-193, Dec. 2003. Bibliography 92 [8] Behzad Razavi, “Design of Integrated Circuits for Optical Communications,” McGRAW-HILL, International Edition 2003. [9] C. K. Yang, and M. A. Horowitz, “A 0.8-um CMOS 2.5-Gbit/s Oversampling Receiver and Transmitter for Serial Links,” IEEE Journal of Solid-State Circuits, vol. 31, no. 12, pp. 2015-2023, Dec. 1996. [10] C. K. Yang, Farjad-Rad, and M. A. Horowitz, “A 0.6um CMOS 4Gb/s Transceiver with Data Recovery using Oversampling,” Symposium on VLSI Circuits Digest of Technical Papers, pp.71-72, 1997. [11] C. K. Yang, Farjad-Rad, and M. A. Horowitz, “A 0.5-um CMOS 4.0-Gbit/s Serial Link Transceiver with Data Recovery Using Oversampling,” IEEE Journal of Solid-State Circuits, vol. 33, no. 5, pp. 713-722, May 1998. [12] T. Lwata, T. Hirata, H. Sugimoto, H. Kimura, and T. Yoshikawa, “A 5Gbps CMOS Frequency Tolerant Multi Phase Clock Recovery Circuit,” Symposium on VLSI Circuits Digest of Technical Papers, pp.83-82, 2002. [13] T. Yoshikawa, T. Yoshida, T. Ebuchi, H. Yamauchi, Matsushita, Electric Industrial Co., Ltd., Osaka, Japan, “A 1.25Gb/s CMOS receiver core with plesiochronous clocking capability for asynchronous burst data acquisition,” IEEE International Solid-State Circuits Conference, pp. 254-255, Feb. 2000. [14] J. G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques, IEEE Journal of Solid-State Circuits, vol.31, no. 11, pp. 1723~1732, Nov. 1996. [15] J. Yuan and C. Svenson, “High-speed CMOS Circuit technique,” IEEE Journal of Solid-State Circuits, vol. 24, pp. 62-70, Feb. 1989. [16] A. Yukawa, “A CMOS 8-bit high-speed A/D converter IC,” IEEE Journal of Solid-State Circuits, vol. 20, no. 3, pp. 775-779, June 1985. [17] R. Farjad-Rad, A CMOS 4-PAM Multi-Gbps Serial Link Transceiver. Ph.D. dissertation, Stanford University, Aug. 2000. [18] M. Mizuno, M. Yamashina, K. Furuta, H. Igura, H.Yamada, et al., “A GHz Bibliography 93 MOS adaptive pipeline technique using MOS current-mode logic,” IEEE Journal of Solid-State Circuits, vol. 31, no. 6, pp. 784-791, June 1996. [19] A. E. Dunlop, W. C. Fischer, M. Banu, and T. Gabara, AT&T Bell Laboratories, Murray Hill, NJ, “150/30 Mb/s CMOS Non-Oversampled Clock and Data Recovery Circuits with instantaneous Locking and Jitter Rejection,” IEEE International Solid-State Circuits Conference, pp. 44-45, Feb. 1995. [20] M. Banu, and A. Dunlop, AT&T Bell Labs, Murray Hill, NJ, “A 660 Mb/s CMOS Clock Recovery Circuit with Instantaneous Locking for NRZ Data and Burst-Mode Transmission,” IEEE International Solid-State Circuits Conference, pp. 102-103, Feb. 1995. [21] Y. Ota, R.G. Swartz, M. Banu, and A.E. Dunlop, “High-Speed, Burst-Mode, Packet-Capable Optical Receiver and Instantaneous Clock Recovery for Optical Bus Operation,” IEEE Journal of Lightwave Technology, vol.12, no. 2, pp. 325-331, Feb. 1994. [22] J. Hwang, C. Park, and C. Park, “155-Mb/s Burst-Mode Clock Recovery Circuit Using the Jitter Reduction Technique,” IEICE Transaction Communication, vol. E86-B, no.4, pp.1423-1426, Apr. 2003. [23] P. Han, and W. Choi, “1Gb/s gated-oscillator burst mode CDR for half-rate clock recovery,” Journal of Semiconductor Technology and Science, vol. 4, no.4, pp. 275-279, Dec. 2004. [24] M. Nogawa, K. Nishimura, S. Kimura, T. Yoshida, T. Kawamura, M. Togashi, K. Kumozaki, and Y. Ohtomo, “A 10Gb/s Burst-Mode CDR IC in 0.13um CMOS,” IEEE International Solid-State Circuits Conference, pp. 228-229, Feb. 2005. [25] Behzad Razavi, ”Design of Analog CMOS Integrated Circuits”, McGraw-Hill, International Edition 2001. [26] Y. A. Eken, and J. P. Uyemura, “A 5.9-G Hz Voltage-Controlled Ring Oscillator in0.18um CMOS,” IEEE Journal of Solid-State Circuits, vol. 39, no. 1, pp. 230-233, Jan. 2004. Bibliography 94 [27] B. Razavi, Y. Ota, and R. G. Swartz, “Design Techniques for Low-Voltage High-Speed Digital Bipolar Circuits,” IEEE Journal of Solid-State Circuits, vol. 29, no. 3, pp. 332-339, March 1994. [28] Yu-Gun KIM, Chun-Oh LEE, Seung-Woo LEE, Hyun-Su CHAI, Hyun-Suk RYU, Woo-Young CHOI, “Novel 622Mb/s Burst-Mode Clock and Data Recovery Circuits with Muxed Oscillators,” IEICE TRANS. COMMUN., vol. E86-B, no. 11, Nov. 2003. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/38248 | - |
| dc.description.abstract | 這篇論文的內容在於，應用於被動光纖網路之突發式時脈資料回復電路的動機、挑戰、和方法。
先介紹為何需要資料時脈回復電路。再來則是對於被動光纖網路的解說，從而了解為何需要突發式的資料時脈回復電路。第一章的重點在於動機，除了動機之外，與突發式資料時脈回復電路相關之被動式光纖網路的規格，也將在這一章當中介紹。 將現有文獻的突發式資料時脈回復電路分為三大類後，分別解說其運作方式。在了解這些基本架構之後，以可達到的傳輸率、鎖定時間、功率、面積、和時間抖動的特性去比較這三大類的優缺點。經過比較之後，將更能清楚地定義出問題，進而提出可行的解決方法。所以，在接下來部分，將介紹兩個所提出的2.5Gbps突發式時脈資料回復電路。 第一個作品為一利用過取樣(Oversampling)的數位形式突發式資料時脈回復電路，其主要是改良自[13]。但我們利用了不同於[13]的演算法，縮短其主要限制操作速度的路徑，而得到更高的傳輸率(2.5Gbps)與低功率消耗(資料時脈回復電路部份33mW)的效果。這一次實作是以0.18微米的標準互補式金氧半製程實現，總面積為1.5mm x 1.01mm。 第二個作品則是利用除頻器產生多頻帶接收能力之突發式時脈資料回復電路。不同於前者的方式，這次所使用的架構並非過取樣，而是利用閘式壓控振盪器(Gated Voltage-Controlled Oscillator)來達到。閘式壓控振盪器即為一可被停止的壓控振盪器，因為其由邏輯閘電路所組成。所以我們將對壓控振盪器作分析，以了解在提高傳輸率至2.5Gbps的同時，將會遭遇到什麼問題，並在之後介紹所提出的閘式壓控振盪器。利用所提出之閘式壓控震盪器和修改過後的除頻器，此電路可接收2488.32Mbps, 1244.16Mbps, 622.08Mbps,及155.52Mbps速率之資料，總功率消耗為70mW。在此次實驗當中，也對Jitter Tolerance作了量測，故在其後對此特性作了分析。此作也是以0.18微米的標準互補式金氧半製程實現，總面積為1.48mm x 0.92mm。 | zh_TW |
| dc.description.abstract | In this thesis, the motivation, challenges, and solutions of burst-mode clock and data recovery (BMCDR) circuits for passive optical networks (PONs) are presented.
The need for clock and data recovery circuits is explained first. Then, the basic architecture of a PON is analyzed so that the BMCDR circuits can be realized. The motivation and the specifications related to BMCDR circuits are also introduced. The existing BMCDR circuits are classified into three categories in this thesis. After introducing every category, a comparison in view of achievable data rate, locking time, power, area, and jitter performance is made. Summarizing the comparisons, the challenges manifest clearly. Thus, two 2.5Gbps BMCDR circuits are presented. Chapter 3 and chapter 4 give the details of these two circuits. A digital-type BMCDR circuit using oversampling is presented. It is modified from [13]. However, with the modified algorithm, the critical path is shortened. A higher-speed (2.5Gbps) and low-power (33mW) BMCDR circuit is obtained. It is implemented in a standard 0.18um CMOS process and the area is 1.5mm x 1.01mm. Besides the former circuit, a multi-band BMCDR circuit using frequency dividers is implemented. Instead of oversampling, this work is based on gated voltage-controlled-oscillator (GVCO) that is namely a stoppable VCO because it is composed of logic gates. Before the proposed GVCO, the analysis of VCO is made to understand the problem encountered when designing a 2.5Gbps GVCO-based BMCDR circuit. With the proposed GVCO and modified frequency dividers, multi-band operation (2488.32Mbps, 1244.16Mbps, 622.08Mbps, and 155.52Mbps) is achieved while consuming 70mW. In addition, the jitter tolerance of this burst-mode CDR circuit is also measured and analyzed. The chip is also implemented in a standard 0.18um CMOS process and the area is 1.48mm x 0.92mm. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T16:28:45Z (GMT). No. of bitstreams: 1 ntu-94-R92943004-1.pdf: 4587674 bytes, checksum: ab69766712fd74d4f239c5c87a1a8f59 (MD5) Previous issue date: 2005 | en |
| dc.description.tableofcontents | 1. Introduction 1
1.1 Why Clock and Data Recovery 1 1.2 Passive Optical Network 3 1.3 Specifications 7 1.3.1 Data rate 7 1.3.2 Locking time 7 1.3.3 Jitter performance 8 1.3.4 Mask of eye diagram for upstream transmission 8 1.4 Thesis Organization 9 2. Categories of Burst-Mode Clock and Data Recovery Circuits 11 2.1 Phase-Locked-Loop-Based Burst-Mode Clock and Data Recovery Circuit 12 2.2 Phase-Picking Burst-Mode Clock and Data Recovery Circuit 16 2.3 Gated Voltage-Controlled Oscillator-Based Burst-Mode Clock and Data Recovery Circuit 19 2.4 Comparison 21 2.4.1 Data rate and locking time 21 2.4.2 Power and area 23 2.4.3 Jitter characteristics 23 2.4.3.1 Jitter transfer 24 2.4.3.2 Jitter tolerance 25 2.4.3.3 Jitter generation 27 2.5 Summary 28 3. A 2.5Gbps Burst-Mode Clock and Data Recovery Circuit Using Oversampling 29 3.1 System Architecture 31 3.2 Building Blocks 32 3.2.1 Phase-Locked Loop 32 3.2.2 Data samplers 34 3.2.3 Edge detectors 35 3.2.4 Clock bit generator 36 3.2.5 Data bit generator 41 3.2.6 Parallel-to-serial circuit & Retiming circuit 43 3.3 Simulation Result 44 3.4 Experimental Result 46 3.5 Performance summary 49 3.6 Conclusion 50 4. A Multi-band Burst-Mode Clock and Data Recovery Circuit Using frequency dividers 51 4.1 System Architecture 52 4.2 Inter-Symbol Interference from Gated Voltage-Controlled Oscillator 54 4.2.1 Inter-symbol interference 54 4.2.2 Configurations of gated voltage-controlled oscillator 55 4.2.3 Non-ideality at Gb/s dta rate 56 4.3 Analysis of Ring Voltage-Controlled Oscillator 59 4.3.1 Conventional analysis 59 4.3.2 Non-linear effect 60 4.4 Proposed Gated Voltage-Controlled Oscillator 68 4.4.1 Configuration 68 4.4.2 Operation 68 4.5 Frequency Divider 72 4.6 Circuit Schematics 75 4.6.1 Delay cell & duty cycle correction buffer 75 4.6.2 Curren-mode logic circuits 76 4.7 Simulation Result 78 4.8 Experimental Result 80 4.9 Analysis of Jitter Tolerance 84 4.10 Performance Summary 87 4.11 Conclusion 88 5. Conclusions and Future Work 89 Bibliography 91 | |
| dc.language.iso | en | |
| dc.title | 應用於被動光纖網路之突發式時脈資料回復電路 | zh_TW |
| dc.title | Burst-Mode Clock and Data Recovery Circuit for Passive Optical Networks | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 93-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 吳介琮,林宗賢,汪重光,陳巍仁 | |
| dc.subject.keyword | 時脈資料回復電路,被動光纖網路,過取樣,閘式壓控振盪器, | zh_TW |
| dc.subject.keyword | CDR,PON,Oversampling,GVCO, | en |
| dc.relation.page | 94 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2005-07-13 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-94-1.pdf 目前未授權公開取用 | 4.48 MB | Adobe PDF |
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