一個操作在0.9伏特電壓的高速雙通道時間交錯連續漸進式類比至數位轉換器

Abstract

近年來，每秒幾億次至十幾億次的中解析度類比至數位轉換器的應用越來越廣泛。本論文提出了一個操作在0.9伏特電壓每秒十五億次取樣的八位元兩通道時間交錯式連續漸進式類比至數位轉換器，是以40奈米CMOS設計。 本論文為了解決時間交錯式類比至數位轉換器的子通道間時脈偏移不匹配問題，提出了一個不需要時脈偏移校正的低時脈偏移的解多工器。為了提高子通道的取樣速度與電能效益，提出了一個使用電荷分配的兩階段連續漸進式類比至數位轉換器與自我觸發閘的技巧。 本時間交錯式連續漸進式類比至數位轉換器在每秒十五億次的取樣速度與奈奎斯特的輸入頻率之下有七點一位元的有效位元，其主動面積只有0.014mm2。功率消耗為3.1mW，達到一個優異的品質因數為15 fJ/conversion-step，其適合用在高電能效益的無線通訊與乙太網路應用中。

Recently, hundreds MS/s to 1GS/s medium resolution Analog-to-Digital Convertors (ADCs) are used extensively in applications. This thesis proposes a 0.9V 8-bit 1.5GS/s two-channel time-interleaved SAR ADC in 40nm CMOS. This thesis proposes a low-skew demultiplexer to solve the timing skew problem between the sub-channels without timing skew calibration. In order to improve the sampling frequency and the energy-efficiency of the sub-channel, the two-step SAR ADC with charge sharing technique and the self-triggered latch technique are proposed. This time-interleaved SAR ADC achieves an ENOB of 7.1 at the conversion rate of 1.5GS/s with Nyquist rate input. The active area is only 0.014 mm2. It consumes 3.1mW and gets the good FoM of 15fJ/conversion-step. It is suitable for the energy-efficient wireless communication and Ethernet network application.