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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳信樹(Hsin-Shu Chen) | |
dc.contributor.author | PO-Chao Huang | en |
dc.contributor.author | 黃柏超 | zh_TW |
dc.date.accessioned | 2021-05-13T08:36:24Z | - |
dc.date.available | 2018-10-14 | |
dc.date.available | 2021-05-13T08:36:24Z | - |
dc.date.copyright | 2016-10-14 | |
dc.date.issued | 2016 | |
dc.date.submitted | 2016-08-13 | |
dc.identifier.citation | [1] H. Huang, et al., “A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS with Passive Residue Transfer,” IEEE ASSCC Dig. Tech. Papers, pp. 289-292, Nov. 2015.
[2] L. Kull, et al., “A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 3049-3058, Dec. 2013. [3] P.-C. Huang, et al., “An 8-bit 900MS/s Two-Step SAR ADC,” IEEE Int. Symp. Circuits and Systems, May. 2016. [4] Y. Duan, et al., “A 12.8 GS/s Time-Interleaved ADC With 25 GHz Effective Resolution Bandwidth and 4.6 ENOB,” IEEE J. Solid-State Circuits, vol. 49, no. 8, pp. 1725-1738, Aug. 2014. [5] Y. Zhu, et al., “An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC,” IEEE ESSCIRC Dig. Tech. Papers, pp. 211-214, Sept. 2014. [6] C.-H. Chan, et al., “A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure,” IEEE Symp. VLSI Circuits, pp. 86-87, June 2012. [7] H.-K. Hong, et al., “A decision-error-tolerant 45nm CMOS 7b 1GS/s nonbinary 2b/cycle SAR ADC,” IEEE J. Solid-State Circuits, vol. 50, no. 2, pp. 543-555, Feb. 2015. [8] N. L. Dortz, et al., “A 1.62GS/s Time-Interleaved SAR ADC with Digital Background Mismatch Calibration Achieving Interleaving Spurs Below 70dBFS” IEEE ISSCC Dig. Tech. Papers, pp. 386-388, February 2014. [9] S. M. Jamal, et al., “Calibration of Sample-Time Error in a Two-Channel Time-Interleaved Analog-to-Digital Converter” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004 [10] T. Jiang, et al., “A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC with Improved Feedback Delay in 40-nm CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 10, pp. 2444-2453, Oct. 2012. [11] F. van der Goes, et al., “A 1.5mW 68dB-SNDR 80MS/s 2-times interleaved SAR-assisted pipelined ADC in 28nm CMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 200-201, Feb. 2014. [12] L. Kull, et al., “A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 378-379, Feb. 2014. [13] L. Kull, et al., “A 35mW 8b 8.8GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32nm Digital SOI CMOS,” IEEE Symp. VLSI Circuits, pp. 260-261, June 2013. [14] E.-Z. Tabasy, et al., “A 6b 10GS/s TI-SAR ADC with Embedded 2-Tap FFE/1-Tap DFE in 65nm CMOS,” IEEE Symp. VLSI Circuits, pp. 274-275, June 2013. [15] P. Schvan, et al., “A 24GS/s 6b ADC in 90nm CMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 544-545, Feb. 2008. [16] R. E. J. van de Grift, et al., “An 8-bit video ADC incorporating folding and interpolation techniques,” IEEE J. Solid-State Circuits, vol. SC-22, no. 6, pp. 944-953, December 1987. [17] H.-Y. Tai, et al., “A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS” IEEE Symp. VLSI Circuits Dig., Jun. 2012, pp. 92-93. [18] C.-C. Lee, et al., “A SAR-Assisted Two-Stage Pipeline ADC,” IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 859-869, April. 2011. [19] Y. Zhu, et al., “A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation,” IEEE J. Solid-State Circuits, vol. 47, no. 11, pp. 2614-2626, Nov. 2012. [20] F. van der Goes, et al., “A 1.5mW 68dB-SNDR 80MS/s 2-times interleaved SAR-assisted pipelined ADC in 28nm CMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 200-201, Feb. 2014. [21] H.-Y. Tai, et al., “A 6-bit 1 GS/s Two-Step SAR ADC in 40 nm CMOS,” IEEE Trans. Circuits and Systems-II: Brief Papers, vol. 61, no. 5, pp. 339-343, May. 2014. [22] C.-C. Liu, et al., “A 10b 100MS/s 1.13mW SAR ADC with Binary-Scaled Error Compensation,” IEEE ISSCC Dig. Tech. Papers, pp. 386-387, Feb. 2010. [23] C.-C. Liu, et al., “A 10-bit 50-MS/s SAR ADC with a Monotonic Capacitor Switching Procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731-740, Apr. 2010. [24] B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGRAW-HILL International Edition, August 2000. [25] Y.-C. Lien, “A 4.5-mW 8-b 750-MS/s 2-b/step Asynchronous Subranged SAR ADC in 28-nm CMOS Technology,” IEEE Symp. VLSI Circuits, pp. 88-89, June 2012. [26] Kenichi Ohhata, et al., “A 1-GHz, 17.5mW, 8-bit Subranging ADC Using Offset Cancelling Charge Steering Amplifier,” IEEE ASSCC Dig. Tech. Papers, pp. 149-152, Nov. 2015. [27] Pieter J. A. Harpe et al., “A 0.47–1.6 mW 5-bit 0.5–1 GS/s Time-Interleaved SAR ADC for Low-Power UWB Radios” IEEE J. Solid-State Circuits, VOL. 47, NO. 7, November 2012 [28] S.-W. M. Chen, et al., “A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2669-2680, Dec. 2006. [29] Ku, et al., “A 40-mW 7-bit 2.2-GS/s Time-Interleaved Subranging CMOS ADC for Low-Power Gigabit Wireless Communications” IEEE J. Solid-State Circuits, VOL. 47, NO. 8, August 2012 [30] V. Hariprasath, et al., “Merged capacitor switching based SAR ADC with highest switching energy-efficiency,” IET Electronics Letters, vol. 46, no. 9, pp. 620-621, April 2010. [31] B. Wicht, et al., “Yield and speed optimization of a latch-type voltage sense amplifier,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1148-1158, July 2004. [32] G.Wegmann, et al., “Charge Injection in Analog MOS Switches” IEEE J. Solid- State Circuits, pp. 1091-1097, December 1987. [33] Y. Ding, et al., “A Universal analytic charge injection model” IEEE Int. Symp. Circuits and Systems, May. 2000. [34] M. V. Elzakker, et al., “A 10-bit Charge-Redistribution ADC Consuming 1.9 uW at 1 MS/s” IEEE J. Solid-State Circuits”, VOL. 45, NO. 5, MAY 2010 [35] M. Gustavsson, et al., “CMOS Data Converters for Communications”, Kluwer Academic Publisher, Boston, 2000 [36] C. Y. Lin, et al., “A 10b 2.6GS/s time-interleaved SAR ADC with background timing skew calibration”, IEEE ISSCC Dig. Tech. Papers, pp. 468-470, Feb. 2016. [37] S. Lee, et al., “A 1GS/s 10b 18.9mW time-interleaved SAR ADC with background timing skew calibration”, IEEE ISSCC Dig. Tech. Papers, pp. 384-386, Feb. 2014. [38] B. R. S. Sung, et al., “A 21fJ/conv-step 9 ENOB 1.6GS/s 2x time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS”, IEEE ISSCC Dig. Tech. Papers, pp. 464-466, Feb. 2015. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/3747 | - |
dc.description.abstract | 近年來,每秒幾億次至十幾億次的中解析度類比至數位轉換器的應用越來越廣泛。本論文提出了一個操作在0.9伏特電壓每秒十五億次取樣的八位元兩通道時間交錯式連續漸進式類比至數位轉換器,是以40奈米CMOS設計。
本論文為了解決時間交錯式類比至數位轉換器的子通道間時脈偏移不匹配問題,提出了一個不需要時脈偏移校正的低時脈偏移的解多工器。為了提高子通道的取樣速度與電能效益,提出了一個使用電荷分配的兩階段連續漸進式類比至數位轉換器與自我觸發閘的技巧。 本時間交錯式連續漸進式類比至數位轉換器在每秒十五億次的取樣速度與奈奎斯特的輸入頻率之下有七點一位元的有效位元,其主動面積只有0.014mm2。功率消耗為3.1mW,達到一個優異的品質因數為15 fJ/conversion-step,其適合用在高電能效益的無線通訊與乙太網路應用中。 | zh_TW |
dc.description.abstract | Recently, hundreds MS/s to 1GS/s medium resolution Analog-to-Digital Convertors (ADCs) are used extensively in applications. This thesis proposes a 0.9V 8-bit 1.5GS/s two-channel time-interleaved SAR ADC in 40nm CMOS.
This thesis proposes a low-skew demultiplexer to solve the timing skew problem between the sub-channels without timing skew calibration. In order to improve the sampling frequency and the energy-efficiency of the sub-channel, the two-step SAR ADC with charge sharing technique and the self-triggered latch technique are proposed. This time-interleaved SAR ADC achieves an ENOB of 7.1 at the conversion rate of 1.5GS/s with Nyquist rate input. The active area is only 0.014 mm2. It consumes 3.1mW and gets the good FoM of 15fJ/conversion-step. It is suitable for the energy-efficient wireless communication and Ethernet network application. | en |
dc.description.provenance | Made available in DSpace on 2021-05-13T08:36:24Z (GMT). No. of bitstreams: 1 ntu-105-R03943045-1.pdf: 2405247 bytes, checksum: 407c07254334f4a5c945b08b8650ec2b (MD5) Previous issue date: 2016 | en |
dc.description.tableofcontents | 摘要……………………………………………………………………….…………… I
Abstract……………………………………………………………………………. ….II Contents……………………………………………………………………………....III List of Figures ………………………………………………………………………...V List of Tables ………………………………………………………………………..VII Chapter 1 Introduction………………………………………………………………...1 1.1Motivation ..1 1.2Thesis Organization ..2 Chapter 2 Fundamentals of Analog-to-Digital Converter………………………….. ....4 2.1 Introduction ..4 2.2 Performance Metrics ..4 2.2.1 Offset and Gain Error 4 2.2.2 Differential and Integral Nonlinearity (DNL and INL) 5 2.2.3 Signal-to-Noise Ratio (SNR) 6 2.2.4 Total Harmonic Distortion (THD) 7 2.2.5 Spurious Free Dynamic Range (SFDR) 7 2.2.6 Signal to Noise and Distortion Ratio (SNDR) 8 2.2.7 Effective Number of Bits (ENOB) 8 2.2.8 Figure of Merit (FoM) 9 2.3 ADC Architectures ..9 2.3.1 Flash Architecture 10 2.3.2 Pipelined Architecture 11 2.3.3 Successive-Approximation-Register (SAR) Architecture 12 2.3.4 Pipelined-SAR Architecture 13 2.3.5 Time-Interleaved Architecture 14 Chapter 3 Time-Interleaved SAR ADC ………………………………………………17 3.1 Introduction 17 3.2 Error Sources in Time-Interleaved ADC Architecture 17 3.2.1 Offset Mismatch 17 3.2.2 Gain Mismatch 19 3.2.3 Timing Skew Mismatch 21 3.3 Proposed Low-Skew Demultiplexer Architecture 25 3.3.1 Principle 25 3.3.2 Low-Skew Demultiplexer 26 3.4 Proposed Two-Step SAR Sub-ADC Architecture 31 3.4.1 Charge sharing technique 31 3.4.2 Self-Triggered Latch technique 37 3.5 Design Consideration 40 3.5.1 Offset Mismatch Error 40 3.5.2 Gain Mismatch Error 41 3.5.3 Switching Method 42 3.5.4 Accuracy Consideration 44 3.5.5 Speed Consideration 63 3.6 Summary 65 Chapter 4 Circuit Implementation…………………………………………...….…... 66 4.1 Introduction 66 4.2 Clock Phase Generator 66 4.3 Two-Step SAR Sub-ADC 68 4.3.1 Comparator 68 4.3.2 SAR Logic 70 4.3.4 Capacitive DAC 71 4.3.5 Charge Sharing Timing Control Logic 72 4.4 Summary 74 Chapter 5 Measurement Results……………………………………………………...75 5.1 Introduction 75 5.3 Test Setup 75 5.4 PCB Design 76 5.5 Measurement Results 78 5.5.1 Static Performance 80 5.5.2 Dynamic Performance 80 5.6 Summary 83 Chapter 6 Conclusions and Future Work…………………………….……………….84 Bibliography …………………………..…………….………….…………………….86 | |
dc.language.iso | en | |
dc.title | 一個操作在0.9伏特電壓的高速雙通道時間交錯連續漸進式類比至數位轉換器 | zh_TW |
dc.title | A 0.9V High-Speed Two-Channel Time-Interleaved SAR ADC | en |
dc.type | Thesis | |
dc.date.schoolyear | 104-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 許雲翔(Yun-Shiang Shu),劉純成(Chun-Cheng Liu) | |
dc.subject.keyword | 類比至數位轉換器,時間交錯式,連續漸進式,高速,高電能效益,低時脈偏移解多工器,兩階段, | zh_TW |
dc.subject.keyword | analog-to-digital converter (ADC),time-interleaved,successive-approximation register (SAR),high speed,energy-efficient,low-skew demultiplexer,two-step, | en |
dc.relation.page | 91 | |
dc.identifier.doi | 10.6342/NTU201601948 | |
dc.rights.note | 同意授權(全球公開) | |
dc.date.accepted | 2016-08-14 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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