百億位元乙太網路系統之互補式金氧半接收機前端電路設計

Abstract

隨著網際網路的快速成長，區域網路（LAN）及廣域網路（WAN）所需要的資料傳輸率已增加到每秒百億位元。和傳統的銅製雙絞線相比，光纖較具有吸引力的優點包括寬頻和低干擾等。因此，光通訊系統被廣泛的使用在高傳輸速率的應用。一般光通訊系統之接收機前端是由轉阻放大器（TIA）和限制放大器（LA）組成。由於接收機的效能主要是由前端電路主宰，因此前端電路的設計相當重要。III-V族及BJT製程因為具有高操作頻率及低雜訊的特性，在過去十年中常被用於實現大部分的高速接收機前端電路。然而隨著近年來製程的發展，CMOS已經足以實現高速電路並具有低成本和高整合性的優點。 本論文介紹了兩個10GBASE-R乙太網路接收機前端電路的積體電路晶片。兩個晶片都是由0.18 μm 1P6M CMOS製程來實現。在這次的設計中，為達到高速的要求而採用數種寬頻設計技巧。第一顆晶片是具有串接架構之轉阻放大器。根據佈局後模擬，轉阻放大器具有55 dBΩ之轉阻值及7.8 GHz之頻寬。有效晶片面積為1.35 x 1.34 mm2，在1.8伏特電壓下其總功率消耗為87毫瓦。第二顆晶片則是採用Cherry-Hooper架構之寬頻增益單級的限制放大器。由模擬結果顯示限制放大器之增益及頻寬分別為53 dB和600 KHz~9.8 GHz，同時量測結果達到符合系統規格的百億位元資料傳輸速率。本晶片之面積為1.83 x 1.53 mm2，在1.8伏特電壓下之總功率消耗為150毫瓦。所有晶片都經由佈局後模擬加以驗證，同時測試考量及所有量測結果也都會呈現於本論文中。

The data rate of the local area network (LAN) and the wide area network (WAN) reaches 10 Gb/s since the Internet expands rapidly. Fiber has many attractive advantages over the traditional copper twisted-pairs, such as the high bandwidth and low sensitivity to interferences, etc. Therefore, the optical communication systems are widely employed to fulfill the demand for the high-speed applications. The receiver front-end of the optical communication system comprises a transimpedance amplifier (TIA) and a limiting amplifier (LA) in general. The receiver performances are dominated by the front-end circuits, so careful design is required. In last decades, most of the high-speed receiver front-end circuits are realized in III-V materials and BJT process due to their high operating frequency and low-noise characteristics. However, modern fabrication technology makes it possible to realize such high-speed circuits over CMOS process with the advantages of low cost and high integration level. In this thesis, two front-end chips of the 10GBASE-R Ethernet receiver are presented. Both chips are fabricated in 0.18 μm 1P6M CMOS technology. For high-speed requirements, several wideband techniques are adopted in the circuit design. Firstly, a TIA with cascaded architecture is realized. According to the post-layout simulations, this TIA has 55 dBΩ transimpedance gain and 7.8 GHz bandwidth. The active area is 1.35 x 1.34 mm2 and the power dissipation is 87 mW at 1.8 V supply voltage. The second chip design is LA, which is implemented by a wideband gain cell with Cherry-Hooper architecture. The simulated gain and bandwidth of the LA are 53 dB and 600 KHz~9.8 GHz, respectively. The measured data rate achieves 10 Gb/s and satisfies the 10GBASE-R Ethernet system specifications. This chip occupies an area of 1.83 x 1.53 mm2 and the power consumption is 150 mW under 1.8 V supply voltage. All the chips are designed and verified with post-layout simulations. Testing considerations and experimental results are also presented.