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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/36669完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 汪重光(Chorng-Kuang Wang) | |
| dc.contributor.author | Tsung-Ying Li | en |
| dc.contributor.author | 李宗穎 | zh_TW |
| dc.date.accessioned | 2021-06-13T08:10:18Z | - |
| dc.date.available | 2008-07-26 | |
| dc.date.copyright | 2005-07-26 | |
| dc.date.issued | 2005 | |
| dc.date.submitted | 2005-07-20 | |
| dc.identifier.citation | [1] Jafar Savoj and Behzad Razavi, “A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector,” IEEE J. Solid-States Circuits, May 2001.
[2] Behzad Razavi, Design of Integrated Circuits for Optical Communication, McGraw Hill, 2003. [3] Eldon Staggs, Steve Rousselle, and Daniel Wu, “Delivering 40 Gbps Optical Communication Systems,” Inspiring High Frequency Design. [4] Paul S. Henry, “Lightwave Primer,” IEEE J. Quantum Electronics, Dec. 1985. [5] Media Access Control (MAC) Parameters, Physical Layers, and Management Parameters for 10Gb/s Operation. IEEE std. 802.3ae, 2002. [6] Richard Perron, “10 Gb/s LAN Networking: Optical Fiber LAN Design Considerations,” NORDX/CDT, Aug. 2001. [7] Intel Corporation, “10 Gigabit Ethernet Technology Overview,” 2003. [8] 10 Gigabut Ethernet Alliance, “10 Gigabit Ethernet Technology Overview White Paper,” May 2001. [9] Ameet Dhillon, Chris DiMinico, and Andy Woodfin, “Optical Fiber and 10 Gigabit Ethernet,” 10 Gigabit Ethernet Alliance, May 2002. [10] Yuriy M. Greshishchev and Peter Schvan, “A 60-dB Gain, 55-dB Dynamic Range, 10-Gb/s Broad-Band SiGe HBT Limiting Amplifier,” IEEE J. Solid-States Circuits, Dec. 1999. [11] Electronic Components, “10 Gbps AGC Transimpedance Amplifier IC,” OKI Electric Industry, 2000. [12] S. Voinigescu, P. Popescu, P. Banens, M. Copeland, G. Fortier, K. Howlett, M. Herod, D.Marchesan, J. Showell, S. Szilagyi, H. Tran, and J. Weng, “Circuits and Technologies for Highly Integrated Optical Networking IC’s at 10 Gb/s to 40 Gb/s,” in Proc. Custom Integrated Circuits Conf., 2002. [13] H.J. Tsai, “10GBASE Ethernet Receiver Front End Design,” M.S. Thesis, National Taiwan Univ., 2003. [14] Alistair Coles and David Cunningham, “Low Overhead Block Coding for Multi-Gb/s Links,” Hewlett-Packard Company, 1998. [15] Rick Walker, Richard Dugan, “Low Overhead Coding Proposal 10GBE Serial Links,” Agilent Technologies, 2000. [16] Geoff Waters, “10 Gigabit Ethernet and the XAUI Interface,” Agilent Technologies, Jan. 2002. [17] David W. Martin, “10 GE Link Design for Scrambled Encode,” Nortel Network, Sep. 1999. [18] Fiber-Optic Encoding, [Online] Available: http://www.sigcon.com/Pubs/edn/ FiberOpticEncoding.htm [19] Serial Killers, [Online] Available: http://www.sigcon.com/Pubs/news/7_07.htm [20] Govind P. Agrawal, Fiber-Optic Communication Systems, John Wiley & Sons, Inc., 2002. [21] Jun Cao, Afshin Momtaz, Kambiz Vakilian, Michael Green, David Chung, Ken-Chee jen, Mario Caresosa, Ben Tan, Ichiro Fujimori, and Armond Hairapetian, “OC-192 Receiver in Standard 0.18 μm CMOS,” ISSCC Dig. Tech. Papers, 2002. [22] Tsutomu Yoshimura, Kimio Ueda, Jun Takasoh, Yoshiki Wada, Toshihide Oka, Harufusa Kondoh, Osamu Chiba, Yoshihumi Azekawa, and Masahiko Ishiwaki, “A 10Gbase Ethernet Transceiver (LAN PHY) in a 1.8 V, 0.18 μm SOI/CMOS technology,” in Proc. Custom Integrated Circuits Conf., 2002. [23] Helen Kim and Jonathan Bauman, “A 12 GHz 30 dB Modular BiCMOS Limiting Amplifier for 10 Gb SONET Receiver,” ISSCC Dig. Tech. Papers, 2000. [24] Helen H. Kim, S. Chandrasekhar, Charles A. Burrus, Jr., and Jon Bauman, “A Si BiCMOS Transimpedance Amplifier for 10-Gb/s SONET Receiver,” IEEE J. Solid-States Circuits, Mar. 2001. [25] Kenichi Ohhata, Toru Masuda, Kazuo Imai, Ryoji Takeyari, and Katsuyoshi Washio, “A Wide-Dynamic-Range, High-Transimpedance Si Bipolar Preamplifier IC for 10 Gb/s Optical Fiber Links,” IEEE J. Solid-States Circuits, Jan. 1999. [26] Joshua Peters, “Design of High Quality Factor Spiral Inductors in RF MCM-D,” M. S. Thesis, MIT, 2004. [27] Behzad Razavi, RF Microelectronics, Prentice Hall, 1998. [28] P.C. Huang, “Analog Front End Architecture and Circuit Design Techniques for High Speed Communication VLSIs,” Ph.D. Dissertation, National Central Univ., 1998. [29] C.S. Liu, “Design and Implementation of Analog Front-end Circuits for Optical Communication Systems,” M. S. Thesis, National Taiwan Univ., 2003. [30] Sunderarajan S. Mohan, Maria del Mar Hershenson, Stephen P. Boyd, and Thomas H. Lee, “Bandwidth Extension in CMOS with Optimized On-Chip Inductors,” IEEE J. Solid-States Circuits, Mar. 2000. [31] Sherif Galal and Behzad Razavi, “10-Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18-μm CMOS Technology,” IEEE J. Solid-States Circuits, Dec. 2003. [32] Chia-Hsin Wu, Chih-Hun Lee, Wei-Sheng Chen, and Shen-Iuan Liu, “CMOS Wideband Amplifiers Using Multiple Inductive-Series Peaking Technique,” IEEE J. Solid-State Circuits, Feb. 2005. [33] Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw Hill, 2001. [34] David M. Pozar, Microwave Engineering, John Wiley & Sons, Inc., 1998. [35] Devendra K. Misra, Radio-Frequency and Microwave Communication Circuits – Analysis and Design, John Wiley & Sons, Inc., 2001. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/36669 | - |
| dc.description.abstract | 隨著網際網路的快速成長，區域網路（LAN）及廣域網路（WAN）所需要的資料傳輸率已增加到每秒百億位元。和傳統的銅製雙絞線相比，光纖較具有吸引力的優點包括寬頻和低干擾等。因此，光通訊系統被廣泛的使用在高傳輸速率的應用。一般光通訊系統之接收機前端是由轉阻放大器（TIA）和限制放大器（LA）組成。由於接收機的效能主要是由前端電路主宰，因此前端電路的設計相當重要。III-V族及BJT製程因為具有高操作頻率及低雜訊的特性，在過去十年中常被用於實現大部分的高速接收機前端電路。然而隨著近年來製程的發展，CMOS已經足以實現高速電路並具有低成本和高整合性的優點。
本論文介紹了兩個10GBASE-R乙太網路接收機前端電路的積體電路晶片。兩個晶片都是由0.18 μm 1P6M CMOS製程來實現。在這次的設計中，為達到高速的要求而採用數種寬頻設計技巧。第一顆晶片是具有串接架構之轉阻放大器。根據佈局後模擬，轉阻放大器具有55 dBΩ之轉阻值及7.8 GHz之頻寬。有效晶片面積為1.35 x 1.34 mm2，在1.8伏特電壓下其總功率消耗為87毫瓦。第二顆晶片則是採用Cherry-Hooper架構之寬頻增益單級的限制放大器。由模擬結果顯示限制放大器之增益及頻寬分別為53 dB和600 KHz~9.8 GHz，同時量測結果達到符合系統規格的百億位元資料傳輸速率。本晶片之面積為1.83 x 1.53 mm2，在1.8伏特電壓下之總功率消耗為150毫瓦。所有晶片都經由佈局後模擬加以驗證，同時測試考量及所有量測結果也都會呈現於本論文中。 | zh_TW |
| dc.description.abstract | The data rate of the local area network (LAN) and the wide area network (WAN) reaches 10 Gb/s since the Internet expands rapidly. Fiber has many attractive advantages over the traditional copper twisted-pairs, such as the high bandwidth and low sensitivity to interferences, etc. Therefore, the optical communication systems are widely employed to fulfill the demand for the high-speed applications. The receiver front-end of the optical communication system comprises a transimpedance amplifier (TIA) and a limiting amplifier (LA) in general. The receiver performances are dominated by the front-end circuits, so careful design is required. In last decades, most of the high-speed receiver front-end circuits are realized in III-V materials and BJT process due to their high operating frequency and low-noise characteristics. However, modern fabrication technology makes it possible to realize such high-speed circuits over CMOS process with the advantages of low cost and high integration level.
In this thesis, two front-end chips of the 10GBASE-R Ethernet receiver are presented. Both chips are fabricated in 0.18 μm 1P6M CMOS technology. For high-speed requirements, several wideband techniques are adopted in the circuit design. Firstly, a TIA with cascaded architecture is realized. According to the post-layout simulations, this TIA has 55 dBΩ transimpedance gain and 7.8 GHz bandwidth. The active area is 1.35 x 1.34 mm2 and the power dissipation is 87 mW at 1.8 V supply voltage. The second chip design is LA, which is implemented by a wideband gain cell with Cherry-Hooper architecture. The simulated gain and bandwidth of the LA are 53 dB and 600 KHz~9.8 GHz, respectively. The measured data rate achieves 10 Gb/s and satisfies the 10GBASE-R Ethernet system specifications. This chip occupies an area of 1.83 x 1.53 mm2 and the power consumption is 150 mW under 1.8 V supply voltage. All the chips are designed and verified with post-layout simulations. Testing considerations and experimental results are also presented. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T08:10:18Z (GMT). No. of bitstreams: 1 ntu-94-R92943014-1.pdf: 12299096 bytes, checksum: 20757c232fa849e7fd31cc80444e1c84 (MD5) Previous issue date: 2005 | en |
| dc.description.tableofcontents | 1.Introduction..........................................1
1.1 Motivations.........................................1 1.2 Thesis Organizations................................2 2.Optical Communication Systems.........................5 2.1 Optical Communication Systems Overview..............5 2.1.1 Fiber Properties.................................5 2.1.2 Data Formats.....................................9 2.2 10GBase Ethernet Architecture......................10 2.2.1 Physical Coding Sublayer (PCS)..................12 2.2.2 Physical Medium Attachment Sublayer(PMA)........13 2.2.3 Physical Medium Dependent Sublayer (PMD)........13 2.2.4 10GBase Ethernet Design Considerations..........14 2.3 Fiber Optic Transceiver...........................15 2.3.1 Semiconductor Technologies for Optical Network..16 2.3.2 Transmitter Building Blocks.....................18 2.3.3 Receiver Building Blocks........................19 2.4 System Characteristics and Specifications.........21 2.4.1 Optical Definitions.............................21 2.4.2 Effect of Low-Pass Filtering....................22 2.4.3 Effect of High-Pass Filtering...................23 2.4.4 Specifications for 10GBASE-R....................24 3.Transimpedance Amplifier.............................27 3.1 Introduction......................................27 3.2 Transimpedance Amplifier Fundamentals.............27 3.2.1 Design Parameters...............................27 3.2.2 Noise Bandwidth.................................32 3.3 Transimpedance Amplifier Topology.................33 3.3.1 Open-Loop TIA...................................33 3.3.2 Feedback TIA....................................35 3.4 Circuit Requirements for 10GBASE-R................37 3.5 Architecture and Circuit Design...................38 3.5.1 Architecture....................................38 3.5.2 Transimpedance Cell.............................39 3.5.3 Single-to-Differential Circuit..................42 3.6 Simulation Results................................43 3.7 Layout............................................46 3.8 Summary...........................................46 4.Limiting Amplifier...................................49 4.1 Introduction......................................49 4.2 Limiting Amplifier Fundamentals...................49 4.2.1 Design Parameters...............................49 4.2.2 Cascaded Gain Stages............................51 4.2.3 AM/PM Conversion................................53 4.3 Wideband Techniques...............................55 4.3.1 Inductive Peaking...............................55 4.3.2 Capacitive Degeneration.........................59 4.3.3 Cherry-Hooper Amplifier.........................61 4.3.4 fT Doublers.....................................63 4.3.5 Comparison of Wideband Techniques...............64 4.4 Circuit Requirements for 10GBASE-R................65 4.5 Architecture and Circuit Design...................66 4.5.1 Architecture....................................66 4.5.2 Gain Cell.......................................68 4.5.3 Output Buffer...................................74 4.5.4 Offset Extractor................................74 4.5.5 Offset Amplifier and Subtractor.................75 4.6 Simulation Results................................75 4.7 Layout............................................80 4.8 Summary...........................................80 5.Experimental Results.................................83 5.1 Measurement of Transimpedance Amplifier...........83 5.1.1 Testing Environment.............................83 5.1.2 Measurement Results.............................86 5.1.3 Performance Summary.............................94 5.2 Measurement of Limiting Amplifier.................94 5.2.1 Testing Environment.............................94 5.2.2 Measurement Results.............................96 5.2.3 Performance Summary............................101 6.Conclusions.........................................103 Bibliography..........................................105 Appendix A RF Layout Considerations and Measurement Techniques............................................109 A.1 RF Layout Considerations.........................109 A.2 Measurement Techniques...........................110 | |
| dc.language.iso | en | |
| dc.subject | 限制放大器 | zh_TW |
| dc.subject | 轉阻放大器 | zh_TW |
| dc.subject | 光通訊前端電路 | zh_TW |
| dc.subject | TIA | en |
| dc.subject | LA | en |
| dc.subject | Optical front-end circuit | en |
| dc.title | 百億位元乙太網路系統之互補式金氧半接收機前端電路設計 | zh_TW |
| dc.title | CMOS Receiver Front-End Circuit Design for 10GBASE Ethernet System | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 93-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 吳介琮(Jieh-Tsorng Wu),劉深淵(Shen-Iuan Liu),黃柏鈞(Po-Chiun Huang) | |
| dc.subject.keyword | 光通訊前端電路,轉阻放大器,限制放大器, | zh_TW |
| dc.subject.keyword | Optical front-end circuit,TIA,LA, | en |
| dc.relation.page | 112 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2005-07-21 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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