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DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 楊哲人 | |
dc.contributor.author | Wei-Lun Hsu | en |
dc.contributor.author | 徐偉倫 | zh_TW |
dc.date.accessioned | 2021-06-13T07:59:50Z | - |
dc.date.available | 2005-07-28 | |
dc.date.copyright | 2005-07-28 | |
dc.date.issued | 2005 | |
dc.date.submitted | 2005-07-22 | |
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/36409 | - |
dc.description.abstract | 利用離子佈植將雜質掺入矽單晶乃現今半導體業最普遍採用的方法之一,而隨著電子元件微型化的趨勢越來越明顯,薄型離子佈植矽元件退火處理後的結構分析越顯得重要。許多研究顯示經過退火之後的離子佈植矽會產生平面缺陷如疊差、雙晶及層狀雙晶,而再結晶層之微結構改變與介面的生成會帶來巨大的影響。
本實驗將研究重點置於離子佈植矽退火後的雙晶結構以及固相磊晶成長的的演變。針對離子佈植矽進行不同時間的退火處理,以場發射式之高解析度穿透式電子顯微鏡觀察其顯微組織。另外本實驗還分析不同佈植能量的離子佈植矽,觀察由能量這個變因所造成的影響。 實驗分別採用150KeV與200KeV以1×1016/㎝2劑量之Ar+佈植於p-type矽單晶後在800℃退火。經過TEM模擬分析,退火後的離子佈植矽會的確產生疊差,以及層狀之奈米級雙晶。隨著退火時間由10min增加至1hr,固相磊晶成長前緣由原先之結晶/非晶介面(分別為270nm與340nm)往試片表面前進。而從1hr之後到4hr之間停止,自4hr到8hr之間則停滯不前,維持在160nm與220nm處。不同的佈植離子濃度分佈對後續之熱處理後的結構有巨大的影響。高佈植能量於在結晶初期則有遲緩的效果由800℃/10 min此一條件可以觀察得到。 | zh_TW |
dc.description.abstract | Ion implantation is the most popular method for doping the silicon wafer in recent semiconductor industry. Following the recent trend of miniaturization of microelectronic devices, microstructure analysis of thin film recrystallized, ion implanted silicon becomes more and more important. Previous research work has indicated that planar defects such as stacking faults, twins, and lamellar nano-twins will formed in ion implanted silicon thin film during annealing. It is known that twin boundaries significantly affect electrical properties of thin films. However, a fundamental knowledge of lamellar nano-twins is not yet been understood.
In this work, more attention has been paid to the nano-twins and the evolution of solid phase epitaxial regrowth in the annealed specimens. Using field emission gun transmission electron microscope, we make microstructure observations upon different annealing cases, which include different annealing time and different implantation energy, to elucidate the micro structural development. Two implantation energies used on p-type silicon wafers are 150KeV and 200KeV, respectively. The dose is 1×1016 Ar+/㎝2 for both cases, and annealing temperature is 800℃. After TEM examination, it is evident that stacking faults and lamellar nano-twins did formed on {111} of ion implanted silicon during annealing. As annealing time increases from 10 min to 1 hr, the solid phase epitaxial regrowth (SPER) front moves from the previous crystalline/amorphous interface, 270 nm and 340 nm in each case, toward specimen surface. SPER front stopped at certain depths for annealing time between 1hr and 4hr, and there were no further movements for annealing time 4hr and 8hr, the SPER front stopped at depth of 160 nm and 220 nm in each case. Different ion concentration distribution along implant direction has a great impact on the subsequent annealing treatment. Higher implantation energy retards the process of recrystallization at the initial stage of annealing (i.e. 10 min @800℃); the corresponding TEM reveals that some amorphous areas still exist. | en |
dc.description.provenance | Made available in DSpace on 2021-06-13T07:59:50Z (GMT). No. of bitstreams: 1 ntu-94-R92527029-1.pdf: 42014305 bytes, checksum: 96ae680702937e78077560581a5f792f (MD5) Previous issue date: 2005 | en |
dc.description.tableofcontents | 1. 前言 1
2. 文獻回顧 3 2.1. 離子佈植 3 2.1.1. 離子佈植的基本理論 4 2.1.2. 離子佈植造成的矽基材損傷 7 2.1.3. 矽基材損傷分類 8 2.1.3.1. 初次缺陷 9 2.1.3.2. 二次缺陷 10 2.1.3.3. 三次缺陷 11 2.1.4. 離子佈植後之熱處理 12 2.2. 再結晶理論與固相磊晶成長 14 2.2.1. 再結晶曲線 14 2.2.2. 成核與成長 16 2.2.2.1. 成核 16 2.2.2.2. 固相磊晶成長 17 3. 實驗流程 31 3.1. 退火處理 31 3.2. 試片製作 32 3.2.1. 試片裁切對黏 32 3.2.2. 試片研磨拋光-第一面 33 3.2.3. 試片研磨拋光-第二面 35 3.2.4. 黏上銅環與取下試片 36 3.2.5. 試片清洗與離子拋光 36 3.3. 顯微組織觀察 37 4. 佈植能量150KeV矽晶之退火組織演化 44 4.1. 原材之組織 44 4.2. 800℃退火10min之組織 46 4.3. 800℃退火1hr之組織 48 4.4. 800℃退火4hr之組織 48 4.5. 800℃退火8hr之組織 50 5. 佈植能量200KeV矽晶之退火組織演化 67 5.1. 原材之組織 67 5.2. 800℃退火10min之組織 67 5.3. 800℃退火1hr之組織 69 5.4. 800℃退火4hr之組織 70 5.5. 800℃退火8hr之組織 71 6. 結論 85 7. 未來工作 88 8. 參考文獻 89 圖目錄 圖 2 1 入射離子與靶材原子碰撞示意圖19 21 圖 2 2 原子核與電子阻擋能力與入射能量之關係19 21 圖 2 3 400KeV Ge+佈植下之能量傳遞分佈 22 圖 2 4 110KeV,5×1015/㎝2,BF2+佈植(001)Si表面非晶質層19 22 圖 2 5 經1000℃退火之2.5MeV,5×1015/㎝2矽佈植晶片內之缺陷19 23 圖 2 6 經800℃退火80KeV,1×1015/㎝2,P+佈植(001)Si晶片內之射程末端缺陷19 23 圖 2 7 經700℃退火之80KeV,2×1016/㎝2,P+佈植(001)Si晶片內之髮夾型差排19 24 圖 2 8 經800℃退火之150KeV,5×1015/㎝2,As+佈植(001)Si晶片之投影射程缺陷19 24 圖 2 9 經1100℃退火之110KeV,5×1015/㎝2,BF2+佈植(001)Si晶片內之含氟氣泡19 25 圖 2 10 經800℃退火之150KeV,5×1015/㎝2,As2+佈植(001)Si橫截面影像19 25 圖 2 11 經800℃退火之110KeV,5×1015/㎝2,BF2+佈植(001)Si之平視影像19 26 圖 2 12 經氧化後矽晶片內所產生之疊差19 26 圖 2 13 經後段製程後,晶片內罩幕邊緣缺陷衍生之超大差排19 27 圖 2 14 再結晶曲線 27 圖 2 15 文獻41中800℃退火10 min所觀察到之層狀雙晶 28 圖 2 16 文獻32中所觀察到的層狀雙晶 28 圖 2 17 文獻45中所提到的雙晶交錯處 29 圖 2 18 (001)矽晶圓佈植BF2+離子,550℃退火114min之橫截面圖 29 圖 2 19 固相磊晶成長示意圖 30 圖 2 20 高斯函數之離子分佈及參數 30 圖 3 1 真空封管 38 圖 3 2 小型電爐 38 圖 3 3 Tripod 39 圖 3 4 Tripod(分解圖) 39 圖 3 5 研磨拋光機 40 圖 3 6 精密離子拋光系統( Precision Ion Polishing System, PIPS ) 40 圖 3 7 Thickness Fringes 41 圖 3 8 Thickness Fringes 41 圖 3 9 試片製作示意圖1 42 圖 3 10 試片製作示意圖2 43 圖 4 1 150KeV原材 51 圖 4 2 150KeV原材 51 圖 4 3 150KeV原材 52 圖 4 4 150KeV原材 52 圖 4 5 150KeV原材 非晶質層 53 圖 4 6 800℃退火10 min 53 圖 4 7 800℃退火10 min 54 圖 4 8 文獻41之原子模型 55 圖 4 9 文獻41之HRTEM影像 55 圖 4 10 800℃退火10 min 56 圖 4 11 800℃退火10 min 56 圖 4 12 800℃退火10 min 57 圖 4 13 圖 4 12框選處之FFT 57 圖 4 14 Microtwin與Matrix之方位關係 58 圖 4 15 雙晶鏡面兩邊的原子對應 58 圖 4 16 文獻47中所提出之雙晶與基地方位關係 59 圖 4 17 800℃退火1 hr 59 圖 4 18 800℃退火1 hr 60 圖 4 19 800℃退火1 hr 60 圖 4 20 800℃退火1 hr 61 圖 4 21 800℃退火1 hr 61 圖 4 22 800℃退火4 hr 62 圖 4 23 800℃退火4 hr 62 圖 4 24 800℃退火4 hr 63 圖 4 25 800℃退火4 hr 63 圖 4 26 800℃退火4 hr Stacking Faults 64 圖 4 27 800℃退火8 hr 64 圖 4 28 800℃退火8 hr Lamellar Microtwins 65 圖 4 29 800℃退火8 hr Lamellar Microtwins 65 圖 4 30 800℃退火8 hr Stacking Faults 66 圖 5 1 200 KeV 原材 72 圖 5 2 800℃退火10 min 72 圖 5 3 800℃退火10 min 73 圖 5 4 800℃退火10 min 73 圖 5 5 800℃退火10 min 74 圖 5 6 800℃退火1 hr 74 圖 5 7 800℃退火1 hr 75 圖 5 8 800℃退火1 hr 75 圖 5 9 800℃退火1 hr Stacking Faults 76 圖 5 10 800℃退火1 hr Stacking Faults 76 圖 5 11 800℃退火4 hr 77 圖 5 12 800℃退火4 hr 77 圖 5 13 800℃退火4 hr多晶區域 78 圖 5 14 800℃退火4 hr層狀微雙晶 79 圖 5 15 800℃退火4 hr 80 圖 5 16 800℃退火4 hr單晶區域 81 圖 5 17 800℃退火4 hr 82 圖 5 18 800℃退火4 hr Stacking Faults 82 圖 5 19 800℃退火8 hr 83 圖 5 20 800℃退火8 hr 83 圖 5 21 800℃退火8 hr 84 | |
dc.language.iso | zh-TW | |
dc.title | 離子佈植矽單晶之退火奈米雙晶組織研究 | zh_TW |
dc.type | Thesis | |
dc.date.schoolyear | 93-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 林招松,陳俊維,陳興時,蔡明欽 | |
dc.subject.keyword | 離子佈植,矽單晶,奈米,雙晶,退火, | zh_TW |
dc.subject.keyword | Ion implantation,silicon,nano,twin,annealing, | en |
dc.relation.page | 92 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2005-07-22 | |
dc.contributor.author-college | 工學院 | zh_TW |
dc.contributor.author-dept | 材料科學與工程學研究所 | zh_TW |
顯示於系所單位: | 材料科學與工程學系 |
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