絕緣體上矽互補式金氧半元件電容特性之二維和三維分析

Abstract

本論文第二章主要是討論窄通道完全解離絕緣體上矽N型金氧半元件在考慮三度空間的邊緣電場效應時之源/汲-閘極電容和閘-源/汲極的電容特性。由三度空間的分析數據得知，當完全解離絕緣體上矽N型金氧半元件的尺寸縮小到通道寬度為0.1μm時，源極邊牆邊緣電容的影響在閘-源極電容(CGS)中所占的比重，比內邊牆邊緣電容(CFIS)和汲極邊牆的邊緣電容(CFDS)的影響比重佔的多。而在考慮閘-汲極電容(CGD)時，汲極邊牆邊緣的電容(C’FDS)分量在所有邊緣效應電容中所佔比重最高。 第三章中討論部分解離絕緣體上矽N型金氧半元件的電容特性與浮動基體造成電流突增效應間的關係。從二度空間的分析數據得知，當直流的電流突增效應發生時，會因為儲存在矽薄膜層中的過量電洞使寄生的雙載子電晶體導通而使得CSG/CDG曲線會有突跳的現象發生。

In chapter 2, this thesis reports the three-dimensional analysis of the gate-source/drain capacitance behavior of a narrow-channel FD SOI NMOS device considering the 3D fringing electric field effects. Based on the 3D simulation results, when the width of the FD SOI NMOS device is scaled down to 0.1μm, the source sidewall fringing capacitance(CFSS) is the most important contribution to the gate-source capacitance (CGS) as compared to the inner oxide fringing capacitance (CFIS)and the drain side fringing capacitance (CFDS). For the gate-drain capacitance (CGD), the drain sidewall fringing capacitance (C’FDS) is the most important. In chapter 3, this thesis reports the floating-body kink-effect related capacitance behavior of nanometer PD SOI NMOS devices. From the 2D simulation results, at the onset of the DC kink effect, there are sudden jumps in the CSG/CDG curves due to the excess holes stored in the thin-film as a result of the turn-on of the bipolar device.