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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/36368完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 郭正邦 | |
| dc.contributor.author | Guei-Syuan Lin | en |
| dc.contributor.author | 林桂萱 | zh_TW |
| dc.date.accessioned | 2021-06-13T07:58:27Z | - |
| dc.date.available | 2005-07-27 | |
| dc.date.copyright | 2005-07-27 | |
| dc.date.issued | 2005 | |
| dc.date.submitted | 2005-07-22 | |
| dc.identifier.citation | [1.1] P.K.Chatterjee, W.R.Hunter, T.C.Holloway, Y.Y.Lin, “The Impact of Scaling Laws on the choice of n-channel or p-channel for MOS VLSI,” IEEE Electron Device Letters, Vol. EDL-1, p.220, Oct. 1980.
[1.2] G.Baccarani, M.R.Wordeman, R.H.Dennard, “Generalized Scaling Theory and Its Application to a 1/4 Micrometer MOSFET Design,” IEEE Trans. Electron Devices, Vol.ED-31, p.452, Apr. 1984. [1.3] R.H.Dennard, F.H.Gaensslen, H.N.Yu, V.L.Rideout, E.Bassous, A.R.Leblanc, “Design of Ion Implanted MOSFETs with Very Small Physical Dimensions,” IEEE J. Solid-State Circuits, Vol.9, p.256, Oct. 1974. [1.4] J.B.Kuo and K.W.Su, “CMOS VLSI Engineering: Silicon-on- Insulator (SOI),” Kluwer Academic: Dordrecht, 1998. [1.5] A.J. Auberton-Herve, “SOI: Materials to Systems,” IEDM Dig., pp. 3-10, 1996 [1.6] S.Kawamura, “Ultra-Thin-Film SOI Technology and its Application to Next Generation CMOS Devices,” IEEE International SOI Conference Dig., pp. 6-7, 1993. [1.7] J.B.Kuo, Y.G.Chen and K.W.Su, “Sidewall-related narrow channel effect in mesa-isolated fully-depleted ultra-thin SOI NMOS devices,” IEEE Electron Device Letters, Vol. 16, Issue 9, pp. 379 – 381, Sept. 1995. [1.8] Karulkar, P.C., “A novel technique for fabrication of fully depleted CMOS devices in ultra-thin SOI films,” Electron Devices, IEEE Transactions on Volume 36, Issue 11, p.2622 Nov 1989. [1.9] J.Y.Choi, R.Sundaresan, J.G.Fossum, “Monitoring Hot-Electron- Induced Degradation of Floating-Body SOI MOSFETs,” IEEE Electron Device Letters, Vol.11, p.156, April 1990. [1.10] J.Y.Choi, J.G.Fossum, “Analysis and Control of Floating-Body Bipolar Effects in Fully Depleted Submicrometer SOI MOSFET’s,” IEEE Trans. Electron Devices, Vol.ED-38, p.1384, June 1991. [1.11] J.P.Colinge, “Reduction of Kink Effect in Thin-Film SOI MOSFET’s,” IEEE Electron Device Letters, Vol.EDL-9, p.97, Feb. 1988. [2.1] J.B.Kuo and S.C.Lin, 'Low-Voltage SOI CMOS Devices and Circuits,' Wiley Inter-science, New York, 2001. [2.2] J.B.Kuo, Y.G.Chen and K.W.Su, 'Sidewall-Related Narrow Channel Effect in Mesa-Isolated Fully-Depleted Ultra-Thin SOI NMOS Devices,' IEEE Electron Device Letters, Vol. 16, No. 9, pp. 379-381, Sept. 1995. [2.3] H.Wang, M.Chan, Y.Wang, and P.K.Ko, 'The Behavior of Narrow-Width MOS-FET's with MESA Isolation,' IEEE Trnas. Electron Devices, Vol. 47, No. 3, pp. 593-600,March 2000. [2.4] K.W.Su and J.B.Kuo, 'Analytical Threshold Voltage Formula Including Narrow Channel Effects for VLSI Mesa-Isolated FD Ultrathin SOI NMOS Devices,' Japanese J. Applied Physics, pp. 4010-4019, Aug. 1995. [2.5] K.W.Su and J.B.Kuo, 'Compact Current Model for Mesa-Isolated FD SOI NMOS Devices Considering Sidewall-Related Narrow Channel Effects,' IEEE SOI Conf. Digest, pp. 84-85, 1997. [2.6] G.Katti, N.DasGupta, and A.DasGupta, 'Threshold Voltage Model for Mesa-Isolated Small Geometry Fully Depleted SOI MOSFETs Based on Analytical Solution of 3-D Poisson's Equation,' IEEE Trans. Electron Devices, Vol. 51, No. 7, pp. 1169-1177, July 2004. [2.7] K.Kumagai, H.Iwaki, A.Yoshino and S.Kurosawa, 'A 3D Analysis of Source/Drain Capacitance in SOI MOSFET for Practical Circuit Design,' IEEE SOI Conf. Proc. pp. 15-16, Oct. 1994. [2.8] Davinci, Three-Dimensional Device Simulator Program, Technology Modeling Asso-ciates, Inc., 1996. [3.1] S.S.Chen and J.B.Kuo, “Analytical Kink Effect Model of PD SOI NMOS Devices Operating in Strong Inversion,” Solid State Electronics, pp. 447-458, March 1997. [3.2] S.C.Lin and J.B.Kuo, “Temperature Dependent Kink Effect Model for PD SOI NMOS Devices,” IEEE Trans. Electron Devices, pp. 254-258, Feb. 1999. [3.3] J.-P.Colinge, “Reduction of Kink Effect in Thin Film SOI MOSFET’s,” IEEE Electron Device Letters, Vol.EDL-9, pp.97, Feb. 1988 [3.4] K.Kato, T.Wada and K.Taniguchi, “Analysis of Kink Characteristics in Silicon-on-Insulator MOSFET’s Using Two-Carrier Modeling,” IEEE Trans. Electron Devices, Vol. 32, No. 2, pp. 458-462, Feb. 1985 [3.5] S.S.Chen and J.B.Kuo, “An Analytical CAD Kink Effect Model of Partially-Depleted SOI NMOS Devices Operating in Strong Inversion,” Solid State Electronics, Vol. 41, No. 3, pp. 447-458, March 1997. [3.6] J.B.Kuo, K.W.Su and S.C.Lin, “Compact MOS/Bipolar Charge- Control Models of Partially-Depleted SOI CMOS Devices For VLSI Circuit Simulation—SOI-Technology (ST)-SPICE,” ESSDERC Dig., pp. 480-483, Sep. 1999. [3.7] D.E.Ward and R.W.Dutton, “A Charge-Oriented Model for MOS Transistor Capacitances,” IEEE J. Solid-State Circuits, Vol.13, p.703, 1978 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/36368 | - |
| dc.description.abstract | 本論文第二章主要是討論窄通道完全解離絕緣體上矽N型金氧半元件在考慮三度空間的邊緣電場效應時之源/汲-閘極電容和閘-源/汲極的電容特性。由三度空間的分析數據得知，當完全解離絕緣體上矽N型金氧半元件的尺寸縮小到通道寬度為0.1μm時，源極邊牆邊緣電容的影響在閘-源極電容(CGS)中所占的比重，比內邊牆邊緣電容(CFIS)和汲極邊牆的邊緣電容(CFDS)的影響比重佔的多。而在考慮閘-汲極電容(CGD)時，汲極邊牆邊緣的電容(C’FDS)分量在所有邊緣效應電容中所佔比重最高。
第三章中討論部分解離絕緣體上矽N型金氧半元件的電容特性與浮動基體造成電流突增效應間的關係。從二度空間的分析數據得知，當直流的電流突增效應發生時，會因為儲存在矽薄膜層中的過量電洞使寄生的雙載子電晶體導通而使得CSG/CDG曲線會有突跳的現象發生。 | zh_TW |
| dc.description.abstract | In chapter 2, this thesis reports the three-dimensional analysis of the gate-source/drain capacitance behavior of a narrow-channel FD SOI NMOS device considering the 3D fringing electric field effects. Based on the 3D simulation results, when the width of the FD SOI NMOS device is scaled down to 0.1μm, the source sidewall fringing capacitance(CFSS) is the most important contribution to the gate-source capacitance (CGS) as compared to the inner oxide fringing capacitance (CFIS)and the drain side fringing capacitance (CFDS). For the gate-drain capacitance (CGD), the drain sidewall fringing capacitance (C’FDS) is the most important.
In chapter 3, this thesis reports the floating-body kink-effect related capacitance behavior of nanometer PD SOI NMOS devices. From the 2D simulation results, at the onset of the DC kink effect, there are sudden jumps in the CSG/CDG curves due to the excess holes stored in the thin-film as a result of the turn-on of the bipolar device. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T07:58:27Z (GMT). No. of bitstreams: 1 ntu-94-R92943052-1.pdf: 2525587 bytes, checksum: bba0f3150ac25e911c8a76004e914a3c (MD5) Previous issue date: 2005 | en |
| dc.description.tableofcontents | 第一章 導論.......................................1
1.1 SOI簡介.......................................1 1.2 FD SOI........................................4 1.3 PD SOI........................................7 1.4 目標..........................................9 第二章 使用高台式隔絕的奈米完全解離絕緣體上矽N型金 氧半元件之邊緣引發之窄通道效應之電容特性分析......11 2.1 簡介..........................................12 2.2 電容特性......................................14 2.2.1 CDG和CSG之電容模擬..........................14 2.2.2 CGS和CGD之電容模擬..........................19 2.3 討論..........................................28 2.4 結論..........................................33 第三章 奈米部分解離絕緣體上矽N型金氧半元件浮動基體電 流突增效應之電容特性分析..........................35 3.1 簡介..........................................35 3.2 電流突增效應..................................37 3.3 電容特性......................................41 3.4 討論..........................................46 3.5 結論..........................................50 第四章 總結.......................................51 參考文獻..........................................53 | |
| dc.language.iso | zh-TW | |
| dc.subject | 扭曲 | zh_TW |
| dc.subject | 浮動基體 | zh_TW |
| dc.subject | 突增 | zh_TW |
| dc.subject | 三度空間 | zh_TW |
| dc.subject | 三維 | zh_TW |
| dc.subject | 電容 | zh_TW |
| dc.subject | 絕緣體上矽 | zh_TW |
| dc.subject | 窄通道 | zh_TW |
| dc.subject | 邊緣 | zh_TW |
| dc.subject | CDG | en |
| dc.subject | SOI | en |
| dc.subject | Capacitance | en |
| dc.subject | 3D | en |
| dc.subject | kink | en |
| dc.subject | PD | en |
| dc.subject | FD | en |
| dc.subject | floating body | en |
| dc.subject | CSG | en |
| dc.subject | CGS | en |
| dc.subject | CGD | en |
| dc.subject | mesa | en |
| dc.subject | narrow channel | en |
| dc.subject | fringing | en |
| dc.title | 絕緣體上矽互補式金氧半元件電容特性之二維和三維分析 | zh_TW |
| dc.title | Analysis of Capacitance Behavior in SOI CMOS Devices Using 2D and 3D Simulation | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 93-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 王維新,林浩雄,賴飛羆,蘇哿暐 | |
| dc.subject.keyword | 絕緣體上矽,電容,三維,三度空間,突增,扭曲,浮動基體,窄通道,邊緣, | zh_TW |
| dc.subject.keyword | SOI,Capacitance,3D,kink,PD,FD,floating body,CSG,CDG,CGS,CGD,mesa,narrow channel,fringing, | en |
| dc.relation.page | 56 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2005-07-23 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-94-1.pdf 未授權公開取用 | 2.47 MB | Adobe PDF |
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