GPS接收機之自動增益控制電路設計

Abstract

GPS系統雖能藉由展頻碼的程序增益，來抵抗ㄧ些寬頻的干擾或是低能量的窄頻干擾，但其仍無法應付更高能量窄頻干擾，因此GPS抗干擾研究已成一重要課題。本研究規劃頻域方法之GPS抗窄頻干擾接收機之整體架構，由於該系統具有高動態範圍之特性，我們進而針對此應用發展出一個具有90dB動態範圍之回饋式且混合信號式自動增益控制器。 為使後端之頻域抗干擾機制運作正常，AGC之增益調節與抗干擾機制中之FFT Window同步。此外，AGC將增益資訊傳給抗干擾機制以作為干擾消除基準參考。 在本AGC之信號路徑中，係採用之晶片AD8963作為VGA，以晶片AD9244作為ADC。AGC之回饋控制路徑係以數位電路方式實現方面，ADC之後的數位濾波器設計採用CSD作為係數表示方式，並利用子段共享技巧使不同係數共用部分電路。此外，峰值偵測機制中的低通濾波器係以CIC架構實現，該架構利用極少的加法器及減法器來實現極高階的FIR濾波器，並根據暫存器長度刪剪( Register Length Pruning)技巧降低CIC濾波器之暫存器長度，將數位電路所需之邏輯元件大幅減少，以上之設計均可達到達節省電路面積、功率及提升電路效率之目標，。 經過定點模式軟體模擬驗證AGC在無干擾環境及連續波單頻干擾、連續波多頻干擾、脈波干擾與掃頻干擾出現時皆達預期運作目標。AGC架構設計完成後，在SOPC設計軟體中撰寫數位電路之Verilog設計檔進行時序模擬及電路評估，而後再將電路合成後所產生之燒錄檔下載至Altera StratixII FPGA電路驗證板中。最後，建構AGC電路實驗平台，並完成硬體整合測試。

GPS system can cope with wideband noise or low power narrowband interference with the processing gain of spreading code. However, GPS system can not reject high power narrowband interference completely. Therefore, anti-jamming technique has become an important issue. This research proposed a frequency domain anti-jamming GPS receiver scheme. Considering the huge dynamic range of the system, the thesis proposed an automatic gain control system which has a dynamic range of 90dB and is of feedback type and mixed-signal type structure. In order to maintain the performance of the anti-jamming device, the time interval of the adjustment of the AGC is synchronized with the FFT window. Moreover, the AGC sends its gain information to the anti-jamming device as the criterion of jamming excision. The signal path in the AGC utilizes the chip AD8963 as the VGA and AD9244 as the ADC. The backward path is implemented with digital circuits. In order to reduce the circuits area and the power consumption, CSD and sub-expression sharing is introduced for digital filter coefficient representation. Moreover, the lowpass filter in the peak detection device is implemented with CIC structure which utilizes a few adders/subtracters to realize high order FIR filter. Furthermore, CIC register length pruning design is introduced to improve circuits efficiency. With software simulation which emulates realistic conditions, the AGC is proven to meet the operation goal in environments with no jamming or in the occurrence of continuous wave interference (CWI), multi-tone CWI, swept CWI, and pulsed CWI. Afterwards, the digital circuits are designed and evaluated with Verilog language in SOPC development software and programmed to Altera StratixII FPGA board. Finally, the AGC hardware integration is completed and verified.