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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 張帆人(Fan-Ren Chang) | |
| dc.contributor.author | Kuan-I Li | en |
| dc.contributor.author | 李冠儀 | zh_TW |
| dc.date.accessioned | 2021-06-13T07:00:56Z | - |
| dc.date.available | 2010-07-31 | |
| dc.date.copyright | 2005-07-31 | |
| dc.date.issued | 2005 | |
| dc.date.submitted | 2005-07-27 | |
| dc.identifier.citation | [1] GP2015 Datasheets- Zarlink: GPS Receiver RF Front-End
[2] GP2021 Datasheets-Zarlink: 12 Channel GPS Correlator [3] AD8369 Datasheets-Analog Devices: 600 MHz, 45 dB Digitally Controlled Variable Gain Amplifier [4] AD9244 Datasheets-Analog Devices: 14-Bit 40/65 MSPS IF Sampling Analog-To-Digital Converter Datasheets [5] E. D. Kaplan: “Understanding GPS: principles and Application” (Artech House, London, 1996.) [6] J. B. Y. Tsui: ‘Fundamentals of global positioning system receivers, a software approach’ (John Wiley & Sons, Canada, 2000.) [7] G. Dimos, T. Upadhyay and T. Jenkins, “Low-cost solution to narrowband GPS interference problem”, Aerospace and Electronics Conference, 1995. NAECON 1995, Proceedings of the IEEE, Vol. 1, pp. 145-153, May 1995. [8] H.O Elwan,. T.B Tarim,.M Ismail,. “Digitally programmable dB-linear CMOS AGC for mixed-signal applications”, Circuits and Devices Magazine, IEEE, Volume 14,Issue 4,July 1998 Page(s):8 - 11 [9] SystemView Profession Edition, v5.0 Build 065, 2004 by ELANIX. [10] QuartusⅡ, Version 2.2 Build 147, 2002 by Altera Corporation. [11] Jefferey H.Reed “Software Radio”,2002 [12] J. M. Khoury, “On the design of constant settling time AGC circuits”, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on Volume 45, Issue 3, March 1998 Page(s):283 - 294 [13] H. C. Chow; I.H. Wang, “High performance automatic gain control circuit using a S/H peak-detector for ASK receiver”, Electronics, Circuits and Systems, 2002. 9th International Conference on Volume 2,15-18 Sept. 2002 Page(s):429 - 432 vol.2 [14] A. Ndili, P. Enge, “GPS receiver autonomous interference detection”, Position Location and Navigation Symposium, IEEE 1998 ,20-23 April 1998 Page(s):123 - 130 [15] I. Martinez G.“AGC circuits theory and design”, 2001 [16] A. Ndidi, Dr. Per Enge,“Receiver Autonomous interference Detection”1997 [17] Q. Du, M. Jiang, Guangquan Lin, Ning Sun,” ALL-digital AGC in CDMA base station receiver”Communication Technology Proceedings, 2003. ICCT 2003. International Conference April 2003 [18] U. Meyer-Baese: ‘Digital Signal Processing with Field Programmable Gate Arrays’ (Springer, 2001.) [19] P. T. Capozza, B. J. Holland, T. M. Hopkinson, and R. L. Landrau “A single-chip narrow-band frequency-domain excisor for a Global Positioning System (GPS) receiver” IEEE J. Solid-State circuits, vol.35, pp. 401-411, Mar. 2000 [20] P. T. Capozza, B. J. Holland, T. M. Hopkinson, C. Li, D. Moulin, P.Pacheco, and R. Rifkin “Measured effects of a narrowband interference suppressor on GPS receivers” in 55th Annu. Meeting, Cambridge, MA,June 25–27, pp, 645–651. 1999. [21] C. C. Lin; M. T. Shieu; C. K. Wang, “A dual-loop automatic gain control for infrared communication system” ,ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on 6-8 Aug. 2002 Page(s):125 - 128 [22] A. V. Oppenheim and R. W. Schafer: ‘Discrete-time Signal Processing’ (Prentice Hall, 1989.) [23] R. L. Peterson, R. E. Ziemer and D. E. Borth: ‘Introduction to Spread-Spectrum Communications’ (Prentice Hall, 1995.) [24] J. O. Coleman “Express coefficients in 13-ary, Radix-4 CSD to Create Computationally Efficient Multiplierless FIR Filers”,2001 [25] L. S. DeBrunner, V. E. DeBrunner, D. Bhogaraju “Defining Canonical Signed Digit Number Systems as Arithmetic Codes”, 2002 [26] L. S. DeBrunner, V. E. DeBrunner, D. Bhogaraju “Using Variable Length 13-ary, Radix-4 CSD Coefficients to Achieve Low-Area Implementations of FIR Filters”, 2002 [27] E.B.Hogenauer “ An Economical Class of Digital Filters for Decimation and Interpolation,” IEEE Transactions on Acoustics, Speech and Signal Processing, 155-162(1981) [28] 莊智清, 黃國興, ‘電子導航,‘ 全華科技圖書股份有限公司, 2001. [29] M. S. Braasch, A.J. Dierendonck, “GPS receiver architectures and measurements” Proceedings of the IEEE, Volume 87,Issue 1,Jan. 1999 Page(s):48 - 64 [30] C.D. Li, “ Design of Narrowband Suppression and Frequency Translation in GPS Receivers”, 2005 [31] A. Peled, “On the hardware implementation of digital signal processors” Acoustics, Speech, and Signal Processing [see also IEEE Transactions on Signal Processing], IEEE Transactions on Volume 24, Issue 1, Feb 1976 Page(s):76 - 86 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/35609 | - |
| dc.description.abstract | GPS系統雖能藉由展頻碼的程序增益，來抵抗ㄧ些寬頻的干擾或是低能量的窄頻干擾，但其仍無法應付更高能量窄頻干擾，因此GPS抗干擾研究已成一重要課題。本研究規劃頻域方法之GPS抗窄頻干擾接收機之整體架構，由於該系統具有高動態範圍之特性，我們進而針對此應用發展出一個具有90dB動態範圍之回饋式且混合信號式自動增益控制器。
為使後端之頻域抗干擾機制運作正常，AGC之增益調節與抗干擾機制中之FFT Window同步。此外，AGC將增益資訊傳給抗干擾機制以作為干擾消除基準參考。 在本AGC之信號路徑中，係採用之晶片AD8963作為VGA，以晶片AD9244作為ADC。AGC之回饋控制路徑係以數位電路方式實現方面，ADC之後的數位濾波器設計採用CSD作為係數表示方式，並利用子段共享技巧使不同係數共用部分電路。此外，峰值偵測機制中的低通濾波器係以CIC架構實現，該架構利用極少的加法器及減法器來實現極高階的FIR濾波器，並根據暫存器長度刪剪( Register Length Pruning)技巧降低CIC濾波器之暫存器長度，將數位電路所需之邏輯元件大幅減少，以上之設計均可達到達節省電路面積、功率及提升電路效率之目標，。 經過定點模式軟體模擬驗證AGC在無干擾環境及連續波單頻干擾、連續波多頻干擾、脈波干擾與掃頻干擾出現時皆達預期運作目標。AGC架構設計完成後，在SOPC設計軟體中撰寫數位電路之Verilog設計檔進行時序模擬及電路評估，而後再將電路合成後所產生之燒錄檔下載至Altera StratixII FPGA電路驗證板中。最後，建構AGC電路實驗平台，並完成硬體整合測試。 | zh_TW |
| dc.description.abstract | GPS system can cope with wideband noise or low power narrowband interference with the processing gain of spreading code. However, GPS system can not reject high power narrowband interference completely. Therefore, anti-jamming technique has become an important issue. This research proposed a frequency domain anti-jamming GPS receiver scheme. Considering the huge dynamic range of the system, the thesis proposed an automatic gain control system which has a dynamic range of 90dB and is of feedback type and mixed-signal type structure.
In order to maintain the performance of the anti-jamming device, the time interval of the adjustment of the AGC is synchronized with the FFT window. Moreover, the AGC sends its gain information to the anti-jamming device as the criterion of jamming excision. The signal path in the AGC utilizes the chip AD8963 as the VGA and AD9244 as the ADC. The backward path is implemented with digital circuits. In order to reduce the circuits area and the power consumption, CSD and sub-expression sharing is introduced for digital filter coefficient representation. Moreover, the lowpass filter in the peak detection device is implemented with CIC structure which utilizes a few adders/subtracters to realize high order FIR filter. Furthermore, CIC register length pruning design is introduced to improve circuits efficiency. With software simulation which emulates realistic conditions, the AGC is proven to meet the operation goal in environments with no jamming or in the occurrence of continuous wave interference (CWI), multi-tone CWI, swept CWI, and pulsed CWI. Afterwards, the digital circuits are designed and evaluated with Verilog language in SOPC development software and programmed to Altera StratixII FPGA board. Finally, the AGC hardware integration is completed and verified. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T07:00:56Z (GMT). No. of bitstreams: 1 ntu-94-R92921014-1.pdf: 3228352 bytes, checksum: dbed4a177922e3a6f9a0c0b298c1a5eb (MD5) Previous issue date: 2005 | en |
| dc.description.tableofcontents | 中文摘要 ………………………………………………………………………..Ⅰ
英文摘要 …………………………………………………………………….... Ⅲ 目錄 ……………………………………………………………………………..V 圖目錄 …..……………………………………………………………………… VIII 表目錄 ………………………………………………………………………….... XI 英文縮寫 ………………………………………………………………………...XII 第一章 緒論 ……………………………………………………………… 1 1.1 研究背景 …………………………………………………………… 1 1.2 研究動機 …………………………………………………………… 5 1.3 主要挑戰與研究方法 ………………………………………………… 5 1.4 論文架構 …………………………………………………………… 7 第二章 GPS訊號特性與接收機架構…………………………………..… 9 2.1 GPS衛星訊號………………………………………………………….. 9 2.2 GPS訊號與雜訊強度分析……………………………………………... 12 2.3 GPS接收機系統架構…………………………………………………... 16 2.4 GPS抗干擾接收機架構 ……………………………………..… ...19 2.4.1 典型GPS接收機架構………………………………………..……19 2.4.2 GPS抗干擾接收機整體架構………………………………………21 第三章 自動增益控制電路 ………………………………….………………27 3.1 簡介 ……………….……………………………………...………27 3.2 自動增益控制電路常見型態……………………………..…………29 3.2.1回饋式自動增益控制電路 (Feedback Type AGC)………….…29 3.2.2前饋式自動增益控制電路(Feed-forward Type AGC)………….…31 3.2.3雙迴路式自動增益控制電路（Dual Loop AGC）……….……32 3.2.4 混合信號式自動增益控制電路（Mixed-mode Type AGC）…..…33 3.3 AGC數學模型……………………………………………………..35 3.3.1 dB-based 線性AGC模型 …………………………………..35 3.3.2非線性AGC模型 ………………………………….…………..37 3.4 提出之自動增益控制電路…………………………………………….39 3.4.1 信號過大(Over Range)判定…………………………..…………..41 3.4.2 數位式VGA增益控制 ………………………….….………..42 3.5取樣頻率及訊號頻譜規劃…………………………….…………………..44 第四章 數位電路實現 ………………………………………………………51 4.1 標準有號字元數值表示法 ……………………………………………..52 4.1.1 使用加/減法器以及位移實現乘法電路 ………………..52 4.1.2 CSD數值表示法………………………………………..53 4.2 子段共享(Sub-expression Sharing)……………..………….……57 4.3 數位低通濾波器之電路實現……………………………………..…59 4.4 以CIC架構實現低通濾波器……………………….……………66 4.5 CIC之暫存器長度刪減(Register Length Pruning)…………..…………70 第五章 軟體模擬………………………………………………………….73 5.1軟體模擬環境設定……………………………………………….73 5.1軟體模擬結果…………………………………………………..77 第六章 硬體整合………………………………………………….91 6.1硬體整合流程簡介…………………………………………………….91 6.1.1FPGA介紹 ……………………………………………….. 91 6.2硬體設計驗證………………………………………………………..93 6.3 AGC硬體整合……………………………………………………………100 第七章 結論與未來展望………………………………………...…………...107 7.1 結論………………………………………………………………………107 7.2 未來展望…………………………………………………………………109 參考文獻……………………………………………………………………..111 | |
| dc.language.iso | zh-TW | |
| dc.subject | 自動增益控制 | zh_TW |
| dc.subject | GPS抗干擾 | zh_TW |
| dc.subject | Automatic Gain Control | en |
| dc.subject | GPS anti-jamming | en |
| dc.title | GPS接收機之自動增益控制電路設計 | zh_TW |
| dc.title | Design of Automatic Gain Control Circuits for GPS Receiver | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 93-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.coadvisor | 曹恆偉 | |
| dc.contributor.oralexamcommittee | 毛偉龍,王立昇,萬自建 | |
| dc.subject.keyword | 自動增益控制,GPS抗干擾, | zh_TW |
| dc.subject.keyword | Automatic Gain Control,GPS anti-jamming, | en |
| dc.relation.page | 113 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2005-07-27 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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|---|---|---|---|
| ntu-94-1.pdf 未授權公開取用 | 3.15 MB | Adobe PDF |
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