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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/35287
Title: | 通用型不規則低密度奇偶檢查碼解碼器架構之研究 Study on a Generic Decoder Architecture for Irregular LDPC codes |
Authors: | Hsiu-Min Lin 林修民 |
Advisor: | 闕志達(Tzi-Dar Chiueh) |
Keyword: | 低密度奇偶檢查碼,內容位址記憶體,廣播式,通用型, LDPC,Low Density Parity Check,CAM,Broadcast,irregular,Generic, |
Publication Year : | 2005 |
Degree: | 碩士 |
Abstract: | 在本論文中,我們提出一個適合使用在通用不規則性低密度奇偶檢查碼(Low Density Parity Check) 的可重置解碼器架構,首先、我們先調查低密度奇偶檢查碼的各種特性、種類和編碼。其次、我們研究各種低密度奇偶檢查碼的解碼演算法並且根據目前打算使用低密度奇偶檢查碼做為通道編碼的通訊系統的規格、如無線區域網路、都會無線網路和百億位元乙太網路等提出一個可以重置的解碼架構。我們使用內容位址記憶體(Content Address Memory)做為廣播式(Broadcast)存取的基本單元,這樣的架構可以變換各種不同的通訊標準來達到通用的目的。我們接下來使用上述的三種通訊規格提出演算法搭配架構來做C的定點數模擬以及硬體描述語言的設計。最後、我們使用FPGA來做整個設計的量測結果。由於實驗室FPGA容量大小的限制,我們另外提出一個比較小的版本來驗證整個架構的可行性,經過實證,我們的架構可以有效的解碼包含上述通訊規格的各種非規則的低密度奇偶檢查碼。 In this paper, we propose a reconfigurable decoder architecture suitable for generic irregular LDPC (Low Density Parity Check) decoding. First of all, we study LDPC property in detail. Secondly, we survey the LDPC various decoding algorithms and propose an architecture that implements the decoding algorithm with reconfigurability according to standard or specification which adopt LDPC as the channel code, such as IEEE 802.11n proposals, IEEE 802.16d and IEEE 802.3an. The architecture is a broadcast-based architecture with Content Address Memory (CAM) that can decode various kinds of parity check matrices. Finally, the decoder has been verified in C and RTL code for three different parity check matrices. FPGA prototyping is also conducted and successfully tested for a case with smaller parity check matrix due to the limitation in the FPGA device. After normal verification and FPGA measurement, our architecture has been demonstrated to decode efficiently. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/35287 |
Fulltext Rights: | 有償授權 |
Appears in Collections: | 電子工程學研究所 |
Files in This Item:
File | Size | Format | |
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ntu-94-1.pdf Restricted Access | 3.56 MB | Adobe PDF |
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