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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 呂學士 | |
| dc.contributor.author | Wei-cheng Lin | en |
| dc.contributor.author | 林偉程 | zh_TW |
| dc.date.accessioned | 2021-06-13T06:17:09Z | - |
| dc.date.available | 2007-02-10 | |
| dc.date.copyright | 2006-02-10 | |
| dc.date.issued | 2006 | |
| dc.date.submitted | 2006-01-27 | |
| dc.identifier.citation | Reference
[1] SeongHwan Cho; Ock, S.; Sang-Hoon Lee; Joon-Suk Lee; “A Low Power Pipelined Analog-to-Digital Converter using Series Sampling Capacitors”, Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on 23-26 May 2005 Page(s):6178 – 618 [2] Miyazaki, D.; Furuta, M.; Kawahito, S.; “A 75mW 10bit 120MSample/s parallel pipeline ADC”, Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European 16-18 Sept. 2003 Page(s):719 - 722 Digital Object Identifier 10.1109/ESSCIRC.2003.1257236 [3]Byung-Moo Min; Kim, P.; Bowman, F.W., III; Boisvert, D.M.; Aude, A.J.; “A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC”, Solid-State Circuits, IEEE Journal of Volume 38, Issue 12, Dec 2003 Page(s):2031 - 2039 Digital Object Identifier 10.1109/JSSC.2003.819166 [4]Timothy M. Hancock, Scott M. Pernia, and Adam C. Zeeb, “A Digitally Corrected 1.5-bit-per-stage Low-Power 80 MSs 10-Bit Pipelined ADC” , University of Michigan,2002. [5]Qi Yu; Xiang-zhan Wang; Ning Ning; Lin Tang; Hong-Bin Li; Mo-hua Yang; “A 10-bit 100MSPS 0.35 /spl mu/m Si CMOS pipeline ADC”, Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on Volume 2, 18-21 Oct. 2004 Page(s):1523 - 1525 vol.2 Digital Object Identifier 10.1109/ICSICT.2004.1436902 [6]劉憲駿，“100MHz 10位元導管式類比數位轉換器之設計”,MS Thesis, NCTU, 2003, June [7]呂宗憲，“適用於IEEE802.11a之管流式類比數位轉換器設計”,MS Thesis,中華 大學, 2004, July [8]Kelvin Boo-Huat Khoo, “PROGRAMMABLE, HIGH-DYNAMIC RANGE SIGMA-DELTA A/D CONVERTERS FOR MULTISTANDARD, FULLY-INTEGRATED RF RECEIVERS”, University of California at Berkeley,1998 [9]黎慧玉 , “應用數位誤差平均技術之導管式類比數位轉換器”,2002, June. [10]Behead Razavi, “Principles of Data Conversion System Design,” IEEE PRESS, 1995. [11]Behead Razavi, “RF Microelectronics,” Prentice Hall, 1998 [12]Le, H.P.; Zayegh, A.; Singh, J., “A 12-bit high performance low cost pipeline ADC,” Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on Volume 2, 14-17 Dec. 2003 Page(s):471 - 474 Vol.2 Digital Object Identifier 10.1109/ICECS.2003.1301824 [13] Waltari, M.; Sumanen, L.; Korhonen, T.; Halonen, K., “A self-calibrated pipeline ADC with 200MHz IF-sampling frontend,” Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International Volume 1, 3-7 Feb. 2002 Page(s):314 - 469 vol.1 Digital Object Identifier 10.1109/ISSCC.2002.993058 [14] Kenneth C. Dyer, Daihong Fu,Stephen H. Lewis, and Paul J. Hurst, “An Analog Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 12, DECEMBER 1998 [15]鄭光偉, “A 1.0V, 10-bit CMOS Pipeline Anolog-to-Digital Converter,” National Taiwan University MS. Thesis, June 2002. [16]黃善君, “The Design and Realization of Digital Calibration in 10-bit 10 MSPS Pipeline ADC,” National Taiwan University MS. Thesis, Jan 2001. [17]陳麒安, “ADC for wireless Biotelemetry System,” National Taiwan University MS. Thesis, Jan 2005. [18]David William Cline, “Noise, Speed, and Power Trade-offs in Pipelined Analog to Digital Converters,” PHD Thesis, University of California at Berkeley [19]Lauri Sumanen, “Pipeline Analog-to-Digital Converters for Wide-Band Wireless Communications,” PHD Dissertation, Helsinki University of Technology, 2002 [20]Yun Chiu, “An Adaptive Filtering Platform for Digitally Calibrated A/D Conversion,” BWRC Winter Retreat 2004, University of California, Berkeley, Jan. 12, 2004 [21]Thomas Byunghak Cho; Paul R. Gray, “A 10 b, 20 MS/s, 35mW Pipeline AD Converter,” IEEE JSSC vol.30, NO.3, March 1995 [22] Bilhan, E.; Estrada-Gutierrez, P.C.; Valero-Lopez, A.Y.; Maloberti, F., “Behavioral model of pipeline ADC by using SIMULINK(R)” Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on 25-27 Feb. 2001 Page(s):147 - 151 Digital Object Identifier 10.1109/SSMSD.2001.914955 [23] Kuyel, T., ‘Linearity testing issues of analog to digital converters,” Test Conference, 1999. Proceedings. International 28-30 Sept. 1999 Page(s):747 - 756 Digital Object Identifier 10.1109/TEST.1999.805804 [24]Degang Chen; Zhongjun Yu; Geiger, R., “An Adaptive, Truly Background Calibration Method for High Speed Pipeline ADC Design,”Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on 23-26 May 2005 Page(s):6190 - 6193 Digital Object Identifier 10.1109/ISCAS.2005.1466054 [25] Yu Lin; Katyal, V.; Geiger, R.; Schlarmann, M., “kT/C Constrained Optimization of Power in Pipeline ADCs,” Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on 23-26 May 2005 Page(s):1968 - 1971 Digital Object Identifier 10.1109/ISCAS.2005.1465000 [26] Gines, A.J.; Peralias, E.J.; Rueda, A., “Full Calibration Digital Techniques for Pipeline ADCs” Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on 23-26 May 2005 Page(s):1976 - 1979 Digital Object Identifier 10.1109/ISCAS.2005.1465002 [27] Goes, J.; Vital, J.C.; Alves, L.; Ferreira, N.; Ventura, P.; Bach, E.; Franca, J.E.; Koch, R., “A low-power 14-b 5 MS/s CMOS pipeline ADC with background analog self-calibration” Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26th European 19-21 Sept. 2000 Page(s):172 – 175 [28] Yun Chiu, “High-Performance Pipeline A/D Converter Design in Deep-Submicron CMOS,” PHD dissertation, UNIVERSITY of CALIFORNIA, BERKELEY, Fall 2004 [29]陳逸民, “Digital Audio/Video Broadcasting-Standard & Receiver Signal Processing,” 中央大學 2005/4/13 [30] Behead Razavi, “Design of Analog CMOS Integrated Circuits,” McGRAW-HILL [31] www.maxim-ic.com [32]David Smalley, “Equalization Concepts:A Tutorial,” Atlanta Regional Technology Center, October 1994 [33]David Johns, “Equalization,” Course slides,University of Toronto,1997 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/34593 | - |
| dc.description.abstract | In recent years, with the rapid growth of information the speed of data rate in communication system needs to be improved. Therefore different architectures of transceiver have been presented for the solution and as the CMOS technology is evolving, those impractical method before now become realizable. In modern trend of SOC, most of the transceiver will adopt a high-speed and high dynamic range ADC in its system block. For example, in the RF system, more emphases are made on the integration and adaptability. For monolithic integration, a homodyne receiver is more suitable. By its feature of channel selection in base-band, the wanted signal channel and detected signal sensitivity can be adapted by using the digital filtering techniques after the zero-IF signal digitized by the ADC. Pipelined ADC is the most suitable architecture since it features of high speed and can have high dynamic range. Besides, with bootstrapping techniques and power optimization, the low voltage operation and low power consumption can be demonstrated.
This thesis will show how to implement a 10-bit pipelined ADC operating under 2.5V supply voltage by using standard TSMC 0.35um CMOS technology and the measurement result. Because the threshold voltage of this technology is not that of the low-threshold voltage process, the design of OPAMP should be careful. The reason is that the NMOS and PMOS in cascade topology are operating near the boundary of saturation which is close to triode region. This may make the OPAMP not have gain high enough. To solve this problem a digital calibration method will be presented. It’s just like an adaptive equalizer to calibrate the nonlinear transfer curve of ADC’s input and output that resulted from non-ideal stage gain. With this method, a ADC suffered from distortion can be compensated so that its linearity will become better. . | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T06:17:09Z (GMT). No. of bitstreams: 1 ntu-95-R92943142-1.pdf: 2597479 bytes, checksum: 1792a93f66664cfb3aa7a9b194f8dedc (MD5) Previous issue date: 2006 | en |
| dc.description.tableofcontents | Content List
Acknowledgment-------------------------------------------------------------------------------I Abstract------------------------------------------------------------------------------------------II Content List------------------------------------------------------------------------------------IV List of Figures--------------------------------------------------------------------------------VII List of Table-----------------------------------------------------------------------------------XII Chapter 1 Introduction------------------------------------------------------------------------1 1-1.Motivation---------------------------------------------------------------------------1 1-2.The Role of ADC and the goal of this design---------------------------------1 Chapter 2 Basic Concept for ADC----------------------------------------------------------4 2-1 Definition of ADC & Quantization Concept---------------------------------4 2-2. Performance evaluation parameters------------------------------------------5 2-2-1.Resolution------------------------------------------------------------------ 6 2-2-2. Nonlinearity----------------------------------------------------------------6 2-2-3. Signal-to-Noise Ratio----------------------------------------------------8 2-3. Review of Different ADC Architectures-------------------------------------11 2-3-1. Flash ADC----------------------------------------------------------------11 2-3-2. SAR ADC ----------------------------------------------------------------12 2-3-3. Delta-sigma ADC--------------------------------------------------------14 2-3-4. two-step ADC------------------------------------------------------------16 2-3-6. Comparison--------------------------------------------------------------16 Chapter 3 Architecture of Pipelined ADC------------------------------------------------18 3-1.Basic pipeline structures--------------------------------------------------------18 3-2.1.5bit pipeline ADC architecture----------------------------------------------21 3-3.Matlab simulink model----------------------------------------------------------25 Chapter 4 Circuit Design for Pipelined ADC--------------------------------------------35 4-1.OPAMP design--------------------------------------------------------------------35 4-1-1.OPAMP’s design flow---------------------------------------------------35 4-1-2.Requirement calculation-----------------------------------------------36 4-1-3.OPAMP topology decision---------------------------------------------40 4-1-4.Bias circuit design-------------------------------------------------------44 4-1-5.OPAMP’s tuning---------------------------------------------------------46 4-2.Sample and Hold circuit--------------------------------------------------------51 4-2-1.Bottom-plate-sampler--------------------------------------------------51 4-2-2.MDAC circuit design---------------------------------------------------55 4-3.Comparator design--------------------------------------------------------------56 4-4.The logic control in MDAC----------------------------------------------------59 4-5.The clock generator and buffer trees----------------------------------------59 4-6.The digital error correction block--------------------------------------------60 4-7.Whole circuit simulation-------------------------------------------------------61 Chapter 5 Measurement--------------------------------------------------------------------63 5-1.Layout-----------------------------------------------------------------------------63 5-1-1.power domains ----------------------------------------------------------63 5-1-2.Differential structure----------------------------------------------------64 5-1-3.Inductance consideration in bonding wires------------------------64 5-1-4.Body contact ring--------------------------------------------------------65 5-2.Measurement----------------------------------------------------------------------66 5-2-1.Measurement Environment Setup------------------------------------66 5-2-2.DNL & INL---------------------------------------------------------------72 5-2-3.Dynamic testing----------------------------------------------------------74 5-2-4.Summary------------------------------------------------------------------74 Chapter 6 Calibration Method-------------------------------------------------------------77 6-1.Concept of Adaptive Calibration----------------------------------------------77 6-2.Matlab simulink model and implementation method---------------------81 Chapter 7 Conclusion-------------------------------------------------------------------------87 7-1.Conclusion-------------------------------------------------------------------------87 Reference-------------------------------------------------------------------------------------- -89 | |
| dc.language.iso | en | |
| dc.subject | 類比數位轉換器 | zh_TW |
| dc.subject | 導管式 | zh_TW |
| dc.subject | 校準 | zh_TW |
| dc.subject | pipeline | en |
| dc.subject | calibration | en |
| dc.subject | adc | en |
| dc.title | 低伏導管式類比數位轉換器和
採用可適性濾波技術之數位校準方法 | zh_TW |
| dc.title | Low-voltage Pipelined ADC and A Calibration Method Using Adaptive Filtering
Technique | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 94-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 孟慶宗,黃榮堂,邱弘緯,李朝政 | |
| dc.subject.keyword | 導管式,類比數位轉換器,校準, | zh_TW |
| dc.subject.keyword | pipeline,calibration,adc, | en |
| dc.relation.page | 91 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2006-01-27 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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