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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/33346完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 王勝德 | |
| dc.contributor.author | Chin Feng Tsai | en |
| dc.contributor.author | 蔡青峰 | zh_TW |
| dc.date.accessioned | 2021-06-13T04:35:45Z | - |
| dc.date.available | 2006-07-28 | |
| dc.date.copyright | 2006-07-28 | |
| dc.date.issued | 2006 | |
| dc.date.submitted | 2006-07-19 | |
| dc.identifier.citation | [1] Jay K. Adams, and Donald E. Thomas, “The design of mixed hardware/software systems, ” in 33rd Design Automation Conference,1996, pp. 515-520.
[2] Frank Vahid, Thuy Dm Le, and Yu-chin Hsu, “A comparison of functional and structural partitioning,” in International Symposium on System Synthesis, 1996, pp. 121-126. [3] P Arato, S Juhasz, ZA Mann, and A Orban, D Papp, “ Hardware-software partitioning in embedded system design,”in Intelligent Signal Processing, 2003 IEEE International Symposiumom on, Date: 4-6 Sept. 2003, pp. 197-202. [4] M. Keating and P. Bricaud, Reuse Methodology Mannual (RMM). 3rd Edition, Acdemic Publisher Group, 2002. [5] IPQA, IP Qualification Guidelines, Dec, 2003. [Online]. Available: http://www.taiwanipgateway.org/IPQ/Public/2003_09_23_Verification_Guideline.pdf [6] MicroBlaze Soft Processor Core. [Online]. Available: http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=micro_blaze [7]Embedded Processor Solutions Overview. [Online]. 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Available:http://www.altera.com/literature/manual/mnl_avalon_spec.pdf [17] T. S. Hall and J. O. Hamblen, “System-on-a-Programmable-Chip Development Platforms in the Classroom,” in IEEE Transactions on Education, pp. 502- 507, Volume: 47, Issue: 4, Nov. 2004 [18] Altera Corporation, “Nios Embedded Processor Software Development Reference Manual,” [Online, Cited 2006 June 15].Available: http://www.altera.com/literature/manual/mnl_niossft.pdf [19] Altera Corporation, “SOPC Builder” [Online, Cited 2006 January 15].Available: http://www.altera.com/products/software/products/sopc/sop-index.html [20] Altera Corporation, “Quartus II Software,” [Online, Cited 2006 June 15].Available: http://www.altera.com/products/software/products/quartus2/qts-index.html [21] Altera Corporation, “Nios II Integrated Development Environment,” [Online, Cited 2006 June 15].Available: http://www.altera.com/products/software/products/Nios II/emb-Nios II_ide.html [22] JPEG committee, JPEG is standardized in ISO/IEC IS 10918-1/2. [Online]. Available: http://www.jpeg.org/ [23] Lara Simsic, “Accelerating algorithm in hardware,” Courtesy of Embedded Systems Programming , Jan 20 2004 [Online, Cited 2006 June 15]. Available: http://www.eetasia.com/ARTICLES/2005JAN/B/2005JAN17_CT_EMS_TA.pdf [24] Altera Corporation, “AN 188: Custom Instructions for the Nios Embedded Processor,” 2002 September, [Online, Cited 2006 June 15].Available: http://www.altera.com/literature/an/an188.pdf [25] Altera Corporation, “Developing Components for SOPC Builder Quartus II 6.0 Handbook,” [Online, Cited 2006 June 15]. Available: www.altera.com/literature/hb/qts/qts_qii54007.pdf [26] Red Hat, Inc., “GNUPro Developer Tools,” [Online]. Available: http://www.redhat.com/software/gnupro [27] Karam S. Chatha and Ranga Vemuri “Hardware-software partition and pipelined scheduling of transformation application of mixed hardware/software system,” IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 3, JUNE 2002 [28]T. Wiangtong, P.Y.K. Cheung, and W. Luk, “Hardware/software codesign a systematic approach targeting data-intensive application,” Signal Processing Magazine, IEEE ,Volume: 22, Issue: 3, pp. 14-22, May, 2005. [29] Altera Corporation, “Stratix II Device Family Data Sheet Stratix II Device Handbook,” Volume 1 Revision, [Online, Cited 2006 June 15]. Available: http://www.altera.com/literature/hb/stx2/stx2_sii51001.pdf [30] Altera Corporation , “Stratix II EP2S60 DSP Development Board Data Sheet,” [Online, Cited 2006 June 15]. Available: www.altera.com/literature/hb/stx2/stx2_sii51001.pdf | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/33346 | - |
| dc.description.abstract | 對於混合軟硬體系統，本篇論文利用基於平台的設計方法去設計硬體加速器，在分割軟硬體的過程我們把焦點放在減少軟硬體的溝通花費，我們設計三種架構的硬體加速器並討論如何去測量溝通花費，使用這測量的結果去切割軟硬體。最後我們去分析得到的效能改進的結果。 | zh_TW |
| dc.description.abstract | Aiming to a mixed software/hardware system, in this thesis, we make use of the platform-based methodology to design hardware accelerators on FPGAs. We focused on reducing the hardware/software communication overheads in partitioning the codes. We design three kinds of hardware accelerators on FPGAs and discuss how to measure communication costs. The result of the measurement is then used to divide the codes in a hardware/software that enhances the performances of software. Finally we analyze the performances of our designs. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T04:35:45Z (GMT). No. of bitstreams: 1 ntu-95-R93921113-1.pdf: 590843 bytes, checksum: 2a6c9580ad6f9bc739ca7772eb6009f9 (MD5) Previous issue date: 2006 | en |
| dc.description.tableofcontents | 目錄
中文摘要 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2 英文摘要 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3 誌謝 - - - - - - - - - - - -- - - - - - - - - -- - - - - - - - -- - - - - - - -- - - - - - -- - - - -- 4 目錄 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 5 圖目錄 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - -7 表目錄 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8 第一章、緒論- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9 1.1研究動機- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -9 1.2研究目標和構想- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -10 1.3論文章節安排 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --10 第二章、相關研究- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -11 2.1基於平台設計(platform-based)概述- - - - - - - - - - - - - - - - - - - - - 11 2.2 FPGA技術- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13 2.2.1 FPGA基本組成- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --14 2.2.2 FPGA設計流程- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- -14 2.3 NIOS II架構和SOPC 概述 - - - - - - - - - - - - - - - - - - - - - - - - - - 16 第三章、方法- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -19 3.1 JPEG 概述- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - -19 3.2軟硬體設計流程- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --21 3.3基於平台硬體加速器設計流程- - - - - - - - - - - - - - - - - - - - - - - - 22 3.4分割因子對切割的影響- - - - - - - - - - - - - - - - - - - - - - - - - - - - - 24 第四章、實作過程和實驗結果- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- 27 4.1實驗說明- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --27 4.2 分析profiling報告- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 27 4.3實驗的架構 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --29 4.3.1計算溝通花費- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --33 4.4 實作JPEG FDCT實驗介紹- - - - - - - - - - - - - - - - - - - - - - - - - --37 4.4.1 JPEG FDCT DATA-FLOW- - - - - - - - - - - - - - - - - - - - - - - --37 4.4.2 ONE-PASS IP 架構- - - - - - - - - - - - - - - - - - - - - - - - - - - --- 37 4.4.3 One-pass IP加量化表- - - - - - - - - - - - - - - - - - - - - - - - -- --- 38 4.5實驗結果 - - - - - - - - - - - - - - - - - - - - - - - - -- - -- - - - - - - - - - - - --39 第五章、結論- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ---43 參考文獻- - - - - - - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - - - - - - - - --44 | |
| dc.language.iso | zh-TW | |
| dc.subject | 溝通花費 | zh_TW |
| dc.subject | 混合軟硬體系統 | zh_TW |
| dc.subject | 基於平台硬體加速器設計方法 | zh_TW |
| dc.subject | 硬體加速器 | zh_TW |
| dc.subject | mixed software/hardware system | en |
| dc.subject | platform-based methodology | en |
| dc.subject | commutation cost | en |
| dc.subject | hardware accelerators | en |
| dc.title | 基於平台的FPGA軟硬體共同設計︰以JPEG 壓縮為例 | zh_TW |
| dc.title | A platform-based HW/SW co-design for FPGA: Using JPEG compression as an example | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 94-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 王凡,洪士灝,施吉昇,林順喜 | |
| dc.subject.keyword | 混合軟硬體系統,基於平台硬體加速器設計方法,硬體加速器,溝通花費, | zh_TW |
| dc.subject.keyword | mixed software/hardware system,platform-based methodology,hardware accelerators,commutation cost, | en |
| dc.relation.page | 47 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2006-07-20 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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