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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 黃鐘揚(Chung-Yang Huang) | |
dc.contributor.author | Min-Kuan Hu | en |
dc.contributor.author | 胡敏寬 | zh_TW |
dc.date.accessioned | 2021-06-13T04:33:23Z | - |
dc.date.available | 2006-07-21 | |
dc.date.copyright | 2006-07-21 | |
dc.date.issued | 2006 | |
dc.date.submitted | 2006-07-20 | |
dc.identifier.citation | [1] Hung Chi Chang, “A Low Branch Penalty Processor Supporting Most MIPS Instructions in 0.18um CMOS Technology”, Master Thesis, August 2005.
[2] David A. Patterson and John L. Hennessy “Computer Organization & Design 2nd Edition”, Morgan Kaufmann. [3] Janick Bergeron, “Writing Testbenches - Functional Verification of HDL Models 2nd Edition”, Kluwer Academic Publishers. [4] Lionel Bening and Harry Foster, “Princile of Verifiable RTL Design – A Functional Coding Style Supporting Verification Processes in Verilog”, Kluwer Academic Publishers. [5] Cadence, “Incisive HDL analysis (HAL) User Guide, Product Version 5.3 April 2004”. [6] Cadence, “Assertion Writing Guide, Product Version 5.5 June 2005”. [7] Cadence, “Formal Verifier User Guide, Product Version 5.5 June 2005”. [8] Synopsys “VCS/VCSi User Guide, Version X-2005.06-SP1 December 2005” [9] Synopsys “VCS/VCS MX Coverage Metrics User Guide, Version X-2005.06-SP1 December 2005”. [10] Yaron Wolfsthal, Rebecca M. Gott, “Formal Verification – Is It Real Enough?”, Design Automation Conference, 2005, pp. 670-671. [11] Umberto Rossi, “Can We Really Do Without the Support of Formal Methods in the Verification of Large Designs?”, Design Automation Conference, 2005, pp. 672-673. [12] Prosenjit Chatterjee, “Streamline Verification Process with Formal Property Verification to Meet Highly Compressed Design Cycle”, Design Automation Conference, 2005, pp. 674-677. [13] Harry D. Foster, Adam C. Krolnik, David J. Lacey, “Assertion-Based Design”, Kluwer Academic Publishers. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/33297 | - |
dc.description.abstract | In modern IC design flow, verification and debugging consume most of the design time. Therefore, it is a good idea to make a verification plan before the design process starts. A verification plan adopts organized and systematic approaches to ensure good quality of the design. A traditional verification plan involves simulation of the design and compares the result with a golden model. However, it suffers from the deficiency in coverage and debugging capability. As the recent verification methodology evolves, various new techniques are proposed. In this thesis we adopted both the traditional approaches and new ones in balance to compensate each other and archive high quality of design.
We conducted our design verification in the Register Transfer Level (RTL). Our objective was to find as many bugs in the RTL as we can so that we may treat it as a golden model for the verification in the later design stages. The design under verification (DUV) was implemented by Hung Chi Chang as his master thesis in GIEE NTU. We took his thesis as the design specification. | en |
dc.description.provenance | Made available in DSpace on 2021-06-13T04:33:23Z (GMT). No. of bitstreams: 1 ntu-95-R93943096-1.pdf: 1969910 bytes, checksum: be2c0f7bc359bea0eeb73c9fb99fba9c (MD5) Previous issue date: 2006 | en |
dc.description.tableofcontents | Table of Contents
Part 1 Introduction of the Design under Verification 1. Architecture of MIPS Processor Design … … … … … … … … … … ... ................ 1 1-1 Instruction Classification … … … … … … … … … … … … … … … .................... 1 1-2 Pipeline … … … … … … … … … … … … … … … … … … … … … … .. ................. 2 1-3 Register and Memory … … … … … … … … … … … … … … … … … ................. 4 1-4 Data Hazard and Forwarding … … … … … … … … … … … … … … . ................ 5 1-5 Branch Hazard and Branch Target Buffer … … … … … … … … ...... ................ 6 2. Verification Plan … … … … … … … … … … … … … … … … … … … … . ................ 7 2-1 Previous Works … … … … … … … … … … … … … … … … … … ....................... 7 2-2 Our Proposed Verification Plan … … … … … … … … … … … … … .................. 8 3. Tools Used in the Verification Plan … … … … … … … … .… … … … ................ 10 Part 2 Verification Effort of the Design 4. Linting … … … … … … … … … … … … … … … … … … … … … … … .................... 11 5. Simulation … … … … … … … … … … … … … … … … … … … … … … .................. 13 5-1 Golden Model … … … … … … … … … … … … … … … … … … … ................... 13 5-2 Directed Simulation … … … … … … … … … … … … … … … … … .................. 16 5-3 Random Simulation … … … … … … … … … … … … … … … … … .................. 18 5-4 Coverage Report… … … … … … … … … … … … … … … … … … ... ................. 22 6. Formal Method … … … … … … … … … … … … … … … … … … … … ................. 25 6-1 Partition of the Design … … … … … … … … … … … … … ....… … .................. 25 6-2 Property List of the Partitioned Component … … … ....… ..… … ................... 25 7. Comparison of Various Methods in the Verification Flow … ......... ................... 37 5 8. Summary and Conclusion … … … … … … … … … … … … … … … … .................... 39 9. References … … … … … … … … … … … … … … … … … … … … … ...… ................... 42 | |
dc.language.iso | en | |
dc.title | 低分支代價MIPS處理器之驗證 | zh_TW |
dc.title | Verification of the Low Branch Penalty MIPS Microprocessor | en |
dc.type | Thesis | |
dc.date.schoolyear | 94-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 江介宏(Jie-Hong Jiang),陳中平(Chung-Ping Chen) | |
dc.subject.keyword | 驗證,正規驗證,MIPS, | zh_TW |
dc.subject.keyword | verification,formal verification,MIPS, | en |
dc.relation.page | 43 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2006-07-20 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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