以屏蔽線插入法為基礎之低功率指令位址匯流排設計

Abstract

當晶片設計進入深次微米世代，金屬導線已逐漸成取代邏輯閘延遲而為效能設計上的瓶頸，尤其當工作頻率達到Giga Hz以上時，除了導線間電容造成的雜訊外，導線間寄生電感帶來的效應更是不可忽視。為了降低導線間寄生效應產生的雜訊及功耗，插入屏蔽線是個有效的方法。本篇論文在同時考慮寄生電容、電感模型下，針對指令位址匯流排提出了一個決定屏蔽線插入位置的演算法。它根據匯流排上每一條位元線的內容變換量以及匯流排全部的總內容變換量，將原先的匯流排分割出數個區塊，再從每個區塊中，利用HSPICE模擬的結果作為準則，找出最佳的屏蔽線插入位置。實驗結果顯示，我們的方法在降低功耗及延遲上，成果大約是SSIA方法的1.6倍。其中當插入四條屏蔽線時，較未插入任何屏蔽線的情況下節省了12.83% 的功耗，在時間延遲上亦減少了1.76%。

With the integrated circuits technology entering the era of deep sub-micron, the interconnections on the chip have become the performance bottleneck. The situation is especially obvious when the operating frequency is at several giga Hz because not only the parasitic capacitances result in noise but also the coupling inductances incur the signal integrity problem. In order to reduce the undesired noise and power consumption caused by parasitic elements between wires, shield insertion is a common and effective approach. In this theme, we proposed an algorithm to decide the shield insertion locations under the consideration of both capacitive and inductive coupling impacts. It partitions the whole instruction address bus into some regions according to the coupling effects between every two adjacent signal wires and finds the best shielding location based on HSPICE simulation results. Experimental results show that our method can reduce the power consumption and delay up to 1.6 times the achievements of SSIA. In the case of four shields, there is a 12.83% reduction on power consumption as well as a 1.76% reduction on delay compared to the case without any shield.