低密度奇偶校驗碼之解碼器的軟硬體分割方式探索

Abstract

One of the difficult problems of hardware/software codesign flow is hardware/software partitioning which decides each component of the system to be implemented as hardware or software. The hw/sw (hardware/software) partitioning determines the performance and hardware resource used of the partitioned system. Hw/sw exploration helps us make the decision. It explores pros and cons of all possible hw/sw partitioned systems. We present a system model and hw/sw communication optimization to explore execution time of a partitioned system more precisely. At the same time, they can improve traditional codesign flow. The system model can reduce hw/sw integration and implementation effort and hw/sw communication optimization can reduce hw/sw communication overhead. Low-Density Parity Check (LDPC) codes have been widely considered as error-correcting codes for next generation communication systems. Therefore, we take LDPC decoder as the case study. After successfully applying our method to LDPC decoder, we can find out different hw/sw partitioned LDPC decoders to satisfy different needs according to the hw/sw exploration results. Finally, we did implement four kinds of hw/sw partitioned LDPC decoders. By analyzing the experiments results, there is a tradeoff between performance, hardware resource and flexibility.