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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/31467完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 顧孟愷(Mong-kai Ku) | |
| dc.contributor.author | Yi-der Lin | en |
| dc.contributor.author | 林宜德 | zh_TW |
| dc.date.accessioned | 2021-06-13T03:13:23Z | - |
| dc.date.available | 2006-08-29 | |
| dc.date.copyright | 2006-08-29 | |
| dc.date.issued | 2006 | |
| dc.date.submitted | 2006-08-21 | |
| dc.identifier.citation | [1] Wayner Wolf, “A Decade of Hardware/Software Codesign”, Computer, Vol. 36, No. 4, pp. 38 – 43, April 2003.
[2] Ralf Niemann, “Hardware/Software Codesign for Data Flow Dominated Embedded Systems”, Kluwer Academic Publishers, 1998. [3] Sudarshan Banerjee and Nikil Dutt, “Efficient Search Space Exploration for HW-SW Partitioning”, Proceedings of the international conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 122 – 127, Sep. 2004. [4] M. Baleani et al., “HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform”, Proceedings of the International Symposium on Hardware/Software Codesign (CODES), pp. 151 – 156, May 2002. [5] The hardware/software codesign Framework, POLIS, http://www-cad.eecs.berkeley.edu/~polis [6] P. Arato, “Hardware-software partitioning in embedded system design”, IEEE International Symposium on Intelligent Signal Processing, pp. 197 – 202, Sep. 2003. [7] E. Riccobene et al., “A SoC design methodology involving a UML 2.0 profile for SystemC”, Proceedings of Design, Automation and Test in Europe (DATE), Vol. 2, pp. 704 – 709, 2005. [8] Open SystemC Initiative (OSCI), http://www.systemc.org [9] UML (Unified Modeling Language), http://www.uml.org [10] R. G. Gallager, “Low-Density Parity-Check Codes”, IEEE Transactions on Information Theory, Vol. 8, pp. 21 – 28, Jan. 1962. [11] D.J.C. MacKay and R.M. Neal, “Near Shannon Limit Performance of Low Density Parity Check Codes”, Electronics Letters, Vol. 33, pp. 457 – 458, March 1997. [12] Jun Heo, “Analysis of Scaling Soft Information on Low Density Parity Check Code”, Electronics Letters, Vol. 39, pp. 219 – 221, Jan. 2003. [13] Jun Heo and Keith M.Chugg, “Optimization of Scaling Soft Information in Iterative Decoding via Density Evolution Methods”, IEEE Transactions on Communications, Vol. 53, pp. 957 – 961, June 2005. [14] Altera Corporation, http://www.altera.com [15] Mentor Graphics Corporation, http://www.mentor.com [16] Qiang Wu et al., “A hierarchical CDFG as intermediate representation for hardware/software codesign”, IEEE Conference on Communications, Circuits and Systems and West Sino Expositions, Vol. 2, pp. 1429 – 1432, July 2002. [17] Tang Lei et al., “CFG in sub-graph matching based HW/SW Co-Design”, IEEE Conference on ASIC, pp. 171 – 174, Oct. 2001. [18] Ravi Namballa et al., “Control and Data Flow Graph Extraction for High-Level Synthesis”, IEEE Computer Society Annual Symposium on VLSI, pp. 187 – 192, Feb. 2004. [19] M.D. Galanis et al., “A partitioning methodology for accelerating applications in hybrid reconfigurable platforms”, Proceedings of Design, Automation and Test in Europe (DATE), Vol. 3, pp. 247 – 252, 2005. [20] Lex (Lexical Analyzer Generator), http://dinosaur.compilertools.net [21] Yi Zou et al., “HW-SW partitioning based on genetic algorithm”, Congress on Evolutionary Computation, Vol. 1, pp. 628 – 633, June 2004. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/31467 | - |
| dc.description.abstract | One of the difficult problems of hardware/software codesign flow is hardware/software partitioning which decides each component of the system to be implemented as hardware or software. The hw/sw (hardware/software) partitioning determines the performance and hardware resource used of the partitioned system. Hw/sw exploration helps us make the decision. It explores pros and cons of all possible hw/sw partitioned systems. We present a system model and hw/sw communication optimization to explore execution time of a partitioned system more precisely. At the same time, they can improve traditional codesign flow. The system model can reduce hw/sw integration and implementation effort and hw/sw communication optimization can reduce hw/sw communication overhead. Low-Density Parity Check (LDPC) codes have been widely considered as error-correcting codes for next generation communication systems. Therefore, we take LDPC decoder as the case study. After successfully applying our method to LDPC decoder, we can find out different hw/sw partitioned LDPC decoders to satisfy different needs according to the hw/sw exploration results. Finally, we did implement four kinds of hw/sw partitioned LDPC decoders. By analyzing the experiments results, there is a tradeoff between performance, hardware resource and flexibility. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T03:13:23Z (GMT). No. of bitstreams: 1 ntu-95-R93922067-1.pdf: 733045 bytes, checksum: 5a4df3113ac241818d9f719481d18197 (MD5) Previous issue date: 2006 | en |
| dc.description.tableofcontents | ACKNOWLEDGEMENTS ii
ABSTRACT iii Table of Contents iv Table of Figures vi List of Tables viii Chapter 1 Introduction 1 1.1 Typical HW/SW Codesign Flow 1 1.2 HW/SW Exploration 3 1.3 LDPC Decoder 4 1.3.1 Tanner Graph and Parity Check Matrix 4 1.3.2 Iterative and Two Phases Decoding Algorithm 6 1.4 Thesis Organization 6 Chapter 2 Related Work 8 2.1 System Modeling 8 2.2 Hardware/Software Partitioning 12 Chapter 3 Hardware/Software Exploration 14 3.1 System Modeling 14 3.2 HW/SW Communication Optimization 15 3.3 HW/SW Exploration 17 Chapter 4 Implementation of LDPC Decoder 20 4.1 Target Platform and Development Environment 20 4.2 HW/SW Exploration of LDPC Decoder 24 4.2.1 System Specification 24 4.2.2 System Modeling 24 4.2.3 HW/SW Communication Optimization 35 4.2.4 HW/SW Exploration 37 4.3 Experimental Results 43 Chapter 5 Conclusion and Future Work 46 5.1 Conclusion 46 5.2 Future Work 47 Reference 48 | |
| dc.language.iso | en | |
| dc.subject | 軟硬體分割 | zh_TW |
| dc.subject | 低密度奇偶校驗碼 | zh_TW |
| dc.subject | hw/sw partitioning | en |
| dc.subject | ldpc | en |
| dc.subject | hardware/software partitioning | en |
| dc.subject | hardware/software codesign | en |
| dc.subject | hardware/software exploration | en |
| dc.subject | hw/sw exploration | en |
| dc.subject | hw/sw codesign | en |
| dc.title | 低密度奇偶校驗碼之解碼器的軟硬體分割方式探索 | zh_TW |
| dc.title | A Hardware/Software Exploration of LDPC Decoder Design | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 94-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 洪士灝(Shih-hao Hung),廖俊睿(Jan-ray Liao),楊佳玲(Chia-lin Yang) | |
| dc.subject.keyword | 軟硬體分割,低密度奇偶校驗碼, | zh_TW |
| dc.subject.keyword | hardware/software partitioning,hardware/software codesign,hardware/software exploration,hw/sw exploration,hw/sw partitioning,hw/sw codesign,ldpc, | en |
| dc.relation.page | 49 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2006-08-22 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
| 顯示於系所單位： | 資訊工程學系 | |
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