操作放大器的良率最佳化技術

Abstract

隨著IC的製程更加先進複雜，電路的尺度更小，電晶體的密度更高、晶片運算速度更快。無論製程技術如何進步，電路參數受到製程影響而漂移的問題仍然存在，當類比電路對效能的要求愈高，受到製程變異的影響也愈大。因此，類比電路的可製造性設計(DFM, Design for Manufacturability) 成本會愈來愈高。 在這篇論文中，我們提出了一個採用調整操作放大器的電晶體參數，以達到電路的效能要求，及評估在製程變異下提升操作放大器的製造良率的方法。使用者提供電路的架構、電晶體參數的初始設計值和電路參數的限制條件，我們實作一個良率分析及最佳化的工具，並且以一個操作放大器電路的例子來驗證這個想法。此方法不僅止於操作放大器，並可以應用在各種不同電路架構之下。

As the IC fabrication technology becomes increasingly complicated with the scaling down of device feature size, the performance requirements and deadlines in analog IC are becoming more and more difficult to satisfy. The cost of DFM (design-for-manufacturability) is getting higher and higher. In this thesis, we propose a method to evaluate the yield of an operational amplifier and to optimize the opamp's manufacturing yield in the existence of process variations, with the designer provided circuit schematic, set of circuit design variables, and the design variable constraints. A yield analysis and optimization tool is implemented and the idea is validated with an example opamp. The proposed approach is not restricted to amplifiers and can be used to optimize the design of other types of circuits as well.