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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃俊郎(Jiun-Lang Huang) | |
| dc.contributor.author | Cheng-Hsiu Ko | en |
| dc.contributor.author | 柯正修 | zh_TW |
| dc.date.accessioned | 2021-06-13T02:46:35Z | - |
| dc.date.available | 2008-10-25 | |
| dc.date.copyright | 2006-10-25 | |
| dc.date.issued | 2006 | |
| dc.date.submitted | 2006-10-12 | |
| dc.identifier.citation | [1] Wojciech M., Andrzaj J. Strojwas, and S. W. Director, “VLSI Yield Prediction and Estimation: A Unified Framework,” IEEE Trans. Computer-Aided Design, vol. 5, no. 1, Jan. 1986, pp. 114-130.
[2] P. Cox, P. Yang and P. Chatterjee, “Statistical modeling for efficient parametric yield estimation of MOS VLSI circuits,” Inernational Electorn Device Meeting, vol. 29, 1983, pp. 242-245. [3] S. W. Director and G. D. Hachtel, “The Simplicial Approximation Approach to Design Centering,” IEEE Trans. Circuits and Systems, vol. 24, issue 7, Jul. 1977, pp. 363-372. [4] Hany L. Abdel-Malek, Abdel-Karim S.O. Hassan, “The Ellipsoidal Technique for Design Centering and Region Approximation,” IEEE Trans. Computer-Aided Design, vol. 10, no. 8, Aug. 1991, pp. 1006-1014. [5] M. Pelgrom, A. Duinmaijer, and A. Welbers, “Matching Properties of MOS Transistors,” IEEE J. Solid-State Circuits, vol. 24, issue 5, 1989, pp. 1433-1439. [6] P M. Vaidya, “A New Algorithm for Minimizing Convex Functions over Convex Sets,” IEEE Foundations of Computer Science, Oct. 1989, pp. 332-337. [7] Duane Boning and S. Nassif, “Models of Process Variations in Device and Interconnect,” Design of High Performance Microprocessor Circuits, IEEE Press, 2000. [8] Duane Boning and S. Nassif, “Models of Process Variations in Device and Interconnect,” Design of High-Performance Microprocessor Circuits, chapter 6, Wiley-IEEE Press, 2000, pp. 98-116. [9] K. Bernstein, K. Carrig, C. Durham, P. Hansen, D. Hogenmiller, E. Nowak, and N. Rohrer, High Speed CMOS Design Styles, 1998. [10] D. J. Frank, Y. Taur, M. Ieong, and H.-S. P. Wong, “Monte Carlo Modeling of Threshold Variation due to Dopant Fluctuations,” IEEE VLSI Technology Symposium, Jun. 1999, pp. 169-170. [11] http://www.veeco.com/appnotes/Minimizing_DE_in_Copper_CMP.pdf [12] Vikas Mehrotra, “Modeling the Effects of Systematic Process Variation,” PHD thesis at the Massachusetts Institute of Technology, May 2001. [13] Teresa Serrano Gotarredona, Bernabe Linares Barranco, “Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation,” Analog Integrated Circuit and Signal Processing, vol. 21, no. 3, Dec. 1999, pp. 271-296. [14] Teresa Serrano Gotarredona, Bernabe Linares Barranco, “A Methodology for MOS Transistor Mismatch Parameter Extraction and Mismatch Simulation,” IEEE International Symposium on Circuits and Systems, vol.4, May 2000, pp. 109-112. [15] Pawel Grybos, “Low Noise Multichannel Integrated Circuits in CMOS,” AGH Uczelniane Wydawnictwa Naukowo-Dydaktyczne Krakow, 2002, pp. 40-76. [16] M. Soma, “A Design-for-Test Methodology for Active Analog Filter,” International Test Conference, Oct. 1993, pp. 183-192. [17] C. Y. Pan and K. T. Cheng, “Pseudorandom Testing for Mixed-Signal Circuits,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 10, Oct. 1997, pp. 1173-1185. [18] S. R. Nassif, A. J. Strojwas, and S. W. Director, “FABRICS II: A Statistically Based IC Fabrication Process Simulator,” IEEE Trans. Computer-Aided Design, vol. 3, no. 1, Jan. 1984, pp. 40-46. [19] G. Biagetti, S. Orcioni, L. Signoracci, C. Turchetti, P. Crippa and M. Alessandrini, “SiSMA: A Statistical Simulator for Mismatch Analysis of MOS ICs”, IEEE International Conference on Computer-Aided Design, Nov. 2002, pp. 490-496. [20] G. Biagetti, S. Orcioni, C. Turchetti, P. Crippa and M. Alessandrini, “SiSMA - A Tool for Efficient Analysis of Analog CMOS Integrated Circuits Affected by Device Mismatch,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 2, Feb. 2004, pp. 192-207. [21] P. Feldmann and S. W. Director, “Accurate and Efficient Evaluation of Circuit Yield and Yield Gradients,” IEEE International Conference on Computer-Aided Design, Nov. 1990, pp. 120-123. [22] P. Feldmann and S. W. Director, “Improved Methods for IC Yield and Quality Optimization Using Surface Integrals,” IEEE International Conference on Computer-Aided Design, Nov. 1991, pp. 158-161. [23] S. W. Pan and Y. H. Hu, “PYFS–A Statistical Optimization Method for Integrated Circuit Yield Enhancement,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 2, Feb. 1993, pp. 296-309. [24] A. Seifi, K. Ponnambalam, and J. Vlach, “A Unified Approach to Statistical Design Centering of Integrated Circuits with Correlated Parameters,” IEEE Trans. Circuits and Systems, vol. 46, issue 1, Jan. 1999, pp. 190-196. [25] C. J. Spanos and S. W. Director, “PROMETHEUS: A Program for VLSI Process Parameter Extraction,” IEEE International Conference on Computer-Aided Design, Nov. 1988, pp. 176-177. [26] I-hao Chen and A. J. Strojwas, “A Methodology for Optimal Test Structure Design,” Custom Integrated Circuits Conferences, vol. 6, issue 4, Jul. 1987, pp. 592-600. [27] K. K. Low and S. W. Director, “A New Methodology for the Design Centering of IC Fabrication Process,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 10. no. 7. Jul. 1991, pp. 895-903. [28] S. S. Sapatnekar, P. M. Vaidya, and S. M. Kang, “Feasible Region Approximation Using Convex Polytopes,” IEEE International Symposium on Circuits and Systems, May 1993, pp. 1786-1789. [29] Dale E. Hocevar, Paul F. Cox, and Ping Yang, “Parametric Yield Optimization for MOS Circuit Blocks,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 7, no. 6, Jun. 1988, pp. 645-658. [30] S. S. Sapatnekar, P.M. Vaidya, and V. B. Rao, “A Convex Programming Approach to Transistor Sizing for CMOS Circuits,” IEEE International Conference on Computer-Aided Design, Nov. 1991, pp. 482-485. [31] S. S. Sapatnekar, P. M. Vaidya, and S. M. Kang, “Convexity-Based Algorithm for Design Centering,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 13, issue 12, Dec. 1994, pp. 1536-1549. [32] S. W. Director and G. D. Hachtel, “The simplicial approximation approach to design centering,” IEEE Trans. Circuits and Systems, vol. 24, issue 7, Jul. 1977, pp. 363-372. [33] A. Prekopa, “Logarithmic concave measures and related topics,” International Conference on Stochastic Programming, Academic Press, 1980, pp. 63-82. [34] C. Y. Pan and K. T. Cheng, “Implicit Functional Testing for Analog Circuits,” IEEE VLSI Test Symposium, Apr. 1996, pp. 489-494. [35] C. Y. Pan and K. T. Cheng, “Pseudorandom Testing for Mixed-Signal Circuits,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 10, Oct. 1997, pp. 1173-1185. [36] C. Y. Pan and K. T. Cheng, “Test Generation for Linear Time-Invariant Analog Circuits,” IEEE Trans. Circuits and Systems – II: Analog and Digital Signal Processing, vol. 46, no. 5, May 1999, pp. 554–564. [37] J. A. Tofte, C. K. Ong, J. L. Huang, and K. T. Cheng, “Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Build-In-Self-Test,” IEEE VLSI Test Symposium, May 2000, pp. 237-246. [38] SAS User's Guide: Statistics, SAS Institute Inc., Cary, N.C., 1982. [39] R. A. Johnson and D. W. Wichern, Applied Multivariate Statistical Analysis, Englewood Cliffs, NJ: Prentice-Hall, 1992. [40] Yang Xu, Xin Li, Kan-Lin Hsiung, S. Boyd, and I. Nausieda, “OPERA: Optimization with Ellipsoidal Uncertainty for Robust Analog IC Design,” Design Automation Conference, Jun. 2005, pp. 632 – 637. [41] Hany L. Abdel-Malek and Abdel-Karim S. O. Hassan, “The Ellipsoidal Technique for Design Centering and Region Approximation,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 10, no. 8, Aug. 1991, pp. 1006-1014. [42] C. J. Spanos and S. W. Director, “Parameter Extraction for Statistical IC Process Characterization,” IEEE Trans. Computer-Aided Design, vol. 5, Jan. 1986, pp. 66-78. [43] Shyh-Chyi Wong, Jyh-Kang Ting, and Shun-Liang Hsu, “Characterization and Modeling of MOS Mismatch in Analog CMOS Technology,” International Conference on Microelectronic Test Structure, Mar. 1995, pp. 171-176. [44] Massimo Conti, Paolo Crippa, Simone Orcioni, and Claudio Turchetti, “Layout-Based Statistical Modeling for the Prediction of the Matching Properties of MOS Transistors,” IEEE Trans. Circuits and Systems, vol. 49, no. 5, May 2002, pp. 680-685. [45] Stratigopoulos, H.-G.D., and Yiorgos Makris, “Bridging the Accuracy of Functional and Machine-Learning-Based Mixed-Signal Testing,” IEEE VLSI Test Symposium, Apr. 2006, pp. 406 - 411. [46] P. N. Variyam and A. Chatterjee, “Enhancing Test effectiveness for Analog Circuits Using Synthesized Measurements,” IEEE VLSI Test Symposium, Apr. 1998, pp. 132-137. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/31379 | - |
| dc.description.abstract | 隨著IC的製程更加先進複雜，電路的尺度更小，電晶體的密度更高、晶片運算速度更快。無論製程技術如何進步，電路參數受到製程影響而漂移的問題仍然存在，當類比電路對效能的要求愈高，受到製程變異的影響也愈大。因此，類比電路的可製造性設計(DFM, Design for Manufacturability) 成本會愈來愈高。
在這篇論文中，我們提出了一個採用調整操作放大器的電晶體參數，以達到電路的效能要求，及評估在製程變異下提升操作放大器的製造良率的方法。使用者提供電路的架構、電晶體參數的初始設計值和電路參數的限制條件，我們實作一個良率分析及最佳化的工具，並且以一個操作放大器電路的例子來驗證這個想法。此方法不僅止於操作放大器，並可以應用在各種不同電路架構之下。 | zh_TW |
| dc.description.abstract | As the IC fabrication technology becomes increasingly complicated with the scaling down of device feature size, the performance requirements and deadlines in analog IC are becoming more and more difficult to satisfy. The cost of DFM (design-for-manufacturability) is getting higher and higher.
In this thesis, we propose a method to evaluate the yield of an operational amplifier and to optimize the opamp's manufacturing yield in the existence of process variations, with the designer provided circuit schematic, set of circuit design variables, and the design variable constraints. A yield analysis and optimization tool is implemented and the idea is validated with an example opamp. The proposed approach is not restricted to amplifiers and can be used to optimize the design of other types of circuits as well. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T02:46:35Z (GMT). No. of bitstreams: 1 ntu-95-R93943109-1.pdf: 1331411 bytes, checksum: c2439b7032f414bcb81b78ebe8432225 (MD5) Previous issue date: 2006 | en |
| dc.description.tableofcontents | Table of Contents
List of Figures v List of Tables vi Chapter 1 Introduction 1 1.1 Corner Models and Monte Carlo Simulation 1 1.2 Past Researches on Yield Optimization 2 1.3 The Proposed Yield Optimization Technique 3 1.4 Thesis Organization 3 Chapter 2 Preliminaries 4 2.1 Sources of Variation 4 2.2 Past Related Works 8 Chapter 3 The Proposed Method 17 3.1 Program Flow 17 3.2 Classification Tree Construction 18 3.3 Design Adjustment 22 Chapter 4 Simulation Results 27 4.1 Environment and Configuration 27 4.2 Data Structure 27 4.3 Experimental Results 29 Chapter 5 Conclusions and Future Work 34 5.1 Conclusions 34 5.2 Future Work 34 REFERENCES 36 | |
| dc.language.iso | en | |
| dc.subject | 良率最佳化 | zh_TW |
| dc.subject | yield optimization | en |
| dc.title | 操作放大器的良率最佳化技術 | zh_TW |
| dc.title | A Yield Optimization Technique for Operational Amplifier | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 95-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李建模(Chien-Mo Li),陳竹一(Jwu-E Chen) | |
| dc.subject.keyword | 良率最佳化, | zh_TW |
| dc.subject.keyword | yield optimization, | en |
| dc.relation.page | 39 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2006-10-16 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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