CMOS接收機前端電路設計與本地振盪自身混波直流偏移抑制

Abstract

為了提供晶片上低損耗的相位產生器，作者設計了單晶式變壓器與正交耦合器並於CMOS製程中下線製作。量測變壓器時所觀察到的穿透損耗在所關切的頻帶下都低於 2.5 dB。從 5.7 GHz 至 5.9 GHz ，正交耦合器可達成 1.3 至 4.8 度的相位誤差、0.7 至 2.5 dB 的振幅誤差、17.0 至 24.1 dB 的邊帶排斥與 3.6 至 4.2 dB 的穿透損耗。 在本論文的關鍵部分中作者敘述了次諧波-混波器的設計與製作，並利用實驗結果來證明次諧波-混波器可避免直接降頻接收機中因本地振盪自身相乘所產生直流偏移。在具有變壓器耦合結構的次諧波-混波器中，作者利用圈數比 1:4 的變壓器來產生10.8 dB 的電壓增益並達成優良的線性度 ( IIP2 = 54.0 dBm 、 IIP3 = 7.9 dBm )。隨後作者也將此種變壓器耦合次諧波-混波器與頻帶可調低雜音放大器和正交耦合器整合在一起，完成了一個 1.8 V 操作的接收機前端。 作者將電感電容對折式堆疊架構運用在低雜音放大器與次諧波-混波器，並成功地在 0.18-μm CMOS 製程下實現一個 1 V 操作的接收機前端。在 45.5 mW 的功率消耗下， 這個 1 V 操作的接收機前端電路於 5.4 GHz 可以呈現 26.2 dB 的電壓增益與 5.2 dB 的雜音指數。此 1 V 電路中本地振盪自身相乘在輸入端所造成的直流偏移低於 -110.7 dBm。作者藉著與前述類似的步驟，利用低臨界電壓電晶體製作了一個 0.5 V 操作的接收機前端。在 19.4 mW 的功率消耗下， 這個 0.5 V 操作的接收機前端電路於 5.6 GHz 可以呈現 17.1 dB 的電壓增益與 8.7 dB 的雜音指數。此 0.5 V 電路中本地振盪自身相乘在輸入端所造成的直流偏移低於 -103.6 dBm。 此電路的正交相位是利用正交耦合器在射頻信號路徑上產生，輸出波形顯示在 5.6 GHz 下的振幅誤差為 0.15 dB，而相位誤差則為 0.01 度。 作者以三維式電感製作了一個 4.5-5.0 GHz 小型化電壓控制振盪器。儘管電感直接位於其他元件的上方，此小型化電壓控制振盪器在 24 mW 的功率消耗下，在與中心頻率 4.9 GHz 差距 1 MHz 處可達成 -122.2 dBc / Hz 的相位雜音。

To provide low-loss on-chip phase generations, monolithic transformers and a quadrature coupler are designed and implemented. The measured insertion losses of the transformers are below 2.5 dB over the band of interest. From 5.7 GHz to 5.9 GHz, the quadrature coupler exhibits phase errors of 1.3 ~ 4.8 degree, magnitude errors of 0.7 ~ 2.5 dB, side-band rejections of 17.0 ~ 24.1 dB and insertion losses of 3.6 ~ 4.2 dB. The key part of this dissertation describes the design and the implementation of subharmonic-mixers (SHMs) along with experimental results showing that the proposed SHMs can prevent the LO-self-mixing DC-offset in direct-conversion receivers. The transformer-coupled configuration is incorporated into SHMs, where a step-up 1:4 transformer is used to contribute a voltage gain of 10.8 dB and achieve excellent linearity (IIP2 of 54.0 dBm and IIP3 of 7.9 dBm). The transformer-coupled SHMs are integrated with a band-variable low-noise-amplifier and the quadrature coupler to develop a 1.8-V receiver front-end. The L-C folded-cascode topology is applied to both LNA and SHM so that a 1-V operation receiver front-end is successfully realized in 0.18-μm CMOS technology. At 5.4 GHz, the 1-V circuit exhibits a voltage gain of 26.2 dB and a noise figure of 5.2 dB while dissipating 45.5 mW from a 1.0-V supply. The achieved input-referred dc-offset due to LO self-mixing is below -110.7 dBm. By means of low-threshold-voltage transistors, a 0.5-V operation receiver front-end is also implemented with similar procedure. The 0.5-V circuit achieves 17.1-dB voltage gain and 8.7-dB noise figure at 5.6 GHz while consuming 19.4 mW from the 0.5-V voltage supply. The input-referred dynamic DC-offset is reduced down to –103.6 dBm. The quadrature generation of the 0.5-V receiver front-end is realized in the RF signal path with the quadrature coupler. The I/Q waveforms present 0.15-dB amplitude mismatch and 0.01° phase error at 5.6 GHz. A miniaturized (0.224 mm2) 4.5~5.0 GHz area-efficient 3-D LC VCO with above-IC inductors is implemented. With inductors directly above the other devices, this VCO shows a measured phase noise of -124.6 dBc / Hz at 1 MHz offset from the 4.9 GHz carrier while dissipating 24 mW.