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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 張耀文 | |
dc.contributor.author | Kai-Chi Hsu | en |
dc.contributor.author | 許凱琦 | zh_TW |
dc.date.accessioned | 2021-06-08T07:12:02Z | - |
dc.date.copyright | 2008-08-04 | |
dc.date.issued | 2008 | |
dc.date.submitted | 2008-07-29 | |
dc.identifier.citation | [1] 741 Type Op-amp, http://en.wikipedia.org/wiki/Operational amplifier
[2] T. C. Chen and Y. W. Chang, “Multilevel Full-Chip Gridless Routing with Applications to Optical Proximity Correction,” IEEE Transactions on Computer- Aided Design, vol. 26, no. 6, pp 1041–1053, June. 2007. [3] C. Chu and Y. C. Wong, “FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design,” IEEE Transactions on Computer-Aided Design, vol. 27, no. 1, pp 70–83, Jan. 2008. [4] J. Cohoon and D. S. Richards, “Optimal Two-Terminal α-β Wire Routing,” Integration, the VLSI Journal, vol. 6, no. 1, pp. 35–57, May 1988. [5] J. Cohn, D. Garrod, R. Rutenbar and L. Carley,“KOAN/ANAGRAM II: New Tools for Device-Level Analog Placement and Routing,” Journal of Solid-State Circuits, vol. 26, no. 3, pp. 330–342, 1991. [6] J. Cong, D. Z. Pan and P. V. Srinivas, “Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization,” in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference, pp 373–378, Jan. 2001. [7] J. Cong and J. Shinnerl, Multilevel Optimization in VLSICAD, Kluwer Academic Publishers, Boston, 2003. [8] D. Garrod, R. Rutenbar, and L. Carley, “Automatic Layout of Custom Analog Cells in ANAGRAM,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 544–547, Nov. 1988. [9] J. Jaja and S. A. Wu, “On Routing Two-Terminal Nets in The Presence of Obstacles,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 8, no. 5, pp. 563–570, May 1989. [10] L. C. Liu, H.-P. Tseng, and C. Sechen, “Chip-Level Area Routing,” in Proceedings of ACM International Symposium on Physical Design, pp. 197–204, April 1998. [11] lp solve Package 5.5, http://lpsolve.sourceforge.net/5.5/ [12] R. E. Lunow, “A Channelless, Multilayer Router,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 667–671, June 1988. [13] A. Margarino, A. Romano, A. De Gloria, F. Curatelli, and P. Antognetti, “A Tile-Expansion Router,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 6, no. 4, pp. 507–517, July 1987. [14] T. Ohtsuki, “Gridless Routers-New Wire Routing Algorithms Based on Computational Geometry,” in Proceedings of IEEE International Conference on Circuits and Systems, pp. 802–809, May 1985. [15] J. Ousterhout, “Corner Stitching: A Data-Structuring Technique for VLSI Layout Tools,” IEEE Transactions on Computer-Aided Design, vol. 3, no. 1, pp. 87–100, 1984. [16] G. Plas, G. Gielen, and W. Sansen, A Computer-Aided Design and Synthesis Environment for Analog Integrated Circuits, Springer, 2002. [17] J. M. Rabaey, Digital Integrated Circuits: A Design Perspective, 2nd Edition, Prentice Hall, 2003. [18] M. Sato, J. Sakanaka, and T. Ohtsuki, “A fast Line-Search Method Based on a Tile Plane,” in IEEE International Symposium on Circuits and Systems, pp. 588–591, May 1987. [19] C. Tsai, S. Chen, and W. Feng, “An H-V Alternating Router,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 11, no. 8, pp. 976–991, August 1992. [20] Y. F. Wu, P. Widmayer, M. D. F. Schlag, and C. K. Wong, “Rectilinear Shortest Paths and Minimum Spanning Trees in the Presence of Rectilinear Obstacles,” IEEE Transactions on Computers, vol. C-36, no. 3, pp. 321–331, March 1987. [21] Z. Xing and R. Kaog, “Shortest Path Search Using Tiles and Piecewise Linear Cost Propagation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 2, pp. 145–158, February 2002. [22] L. Zhang, U. Kleine, R. Raut, and Y. Jiang, “Aladin: A Layout Synthesys Tool for Analog Integrated Circuits” in Processing of Analog Integrated Circuits and Signal, vol. 46, no. 3, pp. 215–230, March 2006. [23] S. Q. Zheng, J. S. Lim, and S. S. Iyengar, “Finding Obstacle-Avoiding Shortest Paths Using Implicit Connection Graphs,” IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, vol. 15, no. 1, pp. 103–110, January 1996. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26484 | - |
dc.description.abstract | In the modern electronic system, most parts of it are designed with digital integrated
circuits, but analog circuits still exist in the system since they are the bridges between the digital circuits and human world. However, in the analog design flow, the automation tools are still very immature. Therefore, the part of the analog design has become the bottleneck of the whole mixed-signal design. To reduce the mismatches of symmetry circuits in the analog circuits which degrade their performance, the designer needs to consider many constraints during layout generation. However, many parameters cannot be extracted directly by just observing the layout polygons. For example, crosstalk noise of a net induced by other neighboring nets needs complex computation, and the complex computation is beyond the designers can handle. In this thesis, we propose an analog circuit routing algorithm considering wirelength minimization and crosstalk noise optimization with analog circuit constraints, length matching and crosstalk matching constraints. We also provide a crosstalk noise model which is suitable for analog circuits. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T07:12:02Z (GMT). No. of bitstreams: 1 ntu-97-R95921039-1.pdf: 612567 bytes, checksum: a31ad6faa2be951c36f2ea5f7bd9f1bd (MD5) Previous issue date: 2008 | en |
dc.description.tableofcontents | Acknowledgements i
Abstract (Chinese) ii Abstract iii List of Tables vi List of Figures vii Chapter 1. Introduction 1 1.1 Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1.1 Routing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1.2 Gridless Routing Algorithm and Data Structure . . . . . . . . . . 4 1.2 Previous Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chapter 2. Crosstalk Model 7 2.1 Enhanced 2-π Crosstalk Noise Model . . . . . . . . . . . . . . . . . . . . 7 2.2 The Characteristics of the Enhanced 2-π Crosstalk Noise Model . . . . . 12 Chapter 3. Problem Description 14 3.1 The AIC Routing Problem with Wirelength Consideration . . . . . . . . 14 3.2 The AIC Routing Problem with Noise Consideration . . . . . . . . . . . 15 Chapter 4. The AIC Routing Algorithm 18 4.1 Algorithm Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 Global Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.1 The Basic ILP Formulation for Wirelength Optimization Problem . 20 4.2.2 The Wirelength-preserving ILP Formulation for Noise Optimization Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3 Detailed Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3.1 Net Position Determination . . . . . . . . . . . . . . . . . . . . . . 34 4.3.2 Local Noise Refinement . . . . . . . . . . . . . . . . . . . . . . . . 40 4.4 Perturbation of Relay Points . . . . . . . . . . . . . . . . . . . . . . . . . 40 Chapter 5. Experiment Results 42 Chapter 6. Conclusions 47 Bibliography 48 | |
dc.language.iso | en | |
dc.title | 類比積體電路佈線自動化與最佳化 | zh_TW |
dc.title | Routing for Analog Integrated Circuits | en |
dc.type | Thesis | |
dc.date.schoolyear | 96-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 林榮彬,王廷基,陳宏明 | |
dc.subject.keyword | 類比電路,自動化,繞線,干擾,長度對秤, | zh_TW |
dc.subject.keyword | analog design,physical design,routing,crosstalk,length matching, | en |
dc.relation.page | 50 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2008-07-31 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
顯示於系所單位: | 電機工程學系 |
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