以低溫多晶矽薄膜電晶體製程實現之全數位式鎖相迴路設計

Abstract

本論文使用3um LTPS TFT製程設計一個全數位式鎖相迴路，用來產生倍頻的時脈，本鎖相迴路的輸出頻率範圍是0.625MHz~12MHz，倍頻範圍是1~30倍，模擬結果時間解析度粗調是5.6ns，微調是0.25ns，而量測結果粗調的時間解析度為8ns。鎖相迴路在電路的應用上是一個重要的模組，近年來發展的潮流也是朝全數位化發展。全數位化的好處是電路對製程的變異性不敏感、電路更改製程容易等。

The thesis presents an all-digital phase-locked loop (ADPLL) as a clock generator implemented in 3um LTPS TFT process. The output frequency range of the ADPLL is from 0.625MHz to 12MHz, the multiplication factors of the reference clock are 1 to 30, and the time resolution of the coarse-tuning part of the DCO is 5.6 ns and that of the fine-tuning part is 0.25ns by simulation. The measuring result of the time resolution of course-tuning part is 8ns. PLL is an essential module in many applications, and the trend of development of PLL is toward all-digital realization. The nature of digital circuits has high immunity against process deviation and it is easy for circuits to be ported among different processes.