請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26261完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 曹恆偉(Hen-Wai Tsao) | |
| dc.contributor.author | Yen-Ting Kuo | en |
| dc.contributor.author | 郭彥廷 | zh_TW |
| dc.date.accessioned | 2021-06-08T07:04:25Z | - |
| dc.date.copyright | 2009-01-20 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-01-12 | |
| dc.identifier.citation | [1] 林嵩鈞，”低溫多晶矽薄膜電晶體元件電容特性之分析”，碩士論文，台灣大學電子工程學研究所，2005年7月
[2] Mark D. Jacunski, Micheal S. Shur, Albert A. Owusu, Trond Ytterdal, Michael Hack, and Benjamin Iniguez, “A Short-Channel DC SPICE Model for Polysilicon Thin-Film Transistors Including Temperature Effects”, IEEE TRANSACTIONS ON ELECTRON DEVICE, VOL. 46, NO. 6, JUNE 1999 [3] Walid Benzarti, Francois Plais, Anthony De Luca, and Didier Pribat, “Compact Analytical Physical-Based Model of LTPS TFT for Active Matrix Displays Addressing Circuits Simulation and Design”, IEEE TRANSACTIONS ON ELECTRON DEVICE, VOL. 51, NO. 3, MARCH 2004 [4] Ming-Dou Ker, Chin-Kang Deng, and Ju-Lin Huang, “On-Panel Output Buffer With Offset Compensation Technique for Data Driver in LTPS Technology”, JOURNAL OF DISPLAY TECHNOLOGY, VOL. 2, NO. 2, JUNE 2006 [5] Jung-Sheng Chen, and Ming-Dou Ker, “New Gate-Bias Voltage-Generating Technology With Threshold-Voltage Compensation for On-Glass Analog Circuits in LTPS Process”, JOURNAL OF DISPLAY TECHNOLOGY, VOL. 3, NO. 3, SEPTEMBER 2007 [6] Satoshi Inoue, Hiroyuki Ohshima, and Tatsuya Shimoda, “Analysis of Degradation Phenomenon Caused by Self-Heating in Low-Temperature-Process Polycrystalline Silicon Thin Film Transistor”, Jpn. J. Appl. Phys. vol. 41, no. 11A, pp. 6313-6319, Nov. 2002 [7] T. Fuyuki, K. Kitajima, H. Yano, T. Hatayama, Y. Uraoka, S. Hashimoto, and Y. Morita, “Thermal Degradation of Low Temperature Poly-Si TFT”, Thin Solid Films, vol. 487, no. 1/2, pp. 216-220, Sep. 2005 [7] 劉深淵，楊清淵，”鎖相迴路”，滄海書局 [8] In-Chul Hwang, Sang-Hun Song, and Soo-Won Kim, “A Digitally Controlled Phase-Locked Loop With a Digital Phase-Frequency Detector for Fast Acquisition” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 10, OCT 2001 [9] Ching-Che Chung and Chen-Yi Lee, ”An All-Digital Phase-Locked Loop for High-Speed Clock Generation ”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 2, FEBRUARY 2003 [10] Pao-Lung Chen, Ching-Che Chung, and Chen-Yi Lee, “A Portable Digitally Controlled Oscillator Using Novel Varactors”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II : EXPRESS BRIEFS, VOL. 52, NO. 5, MAY 2005 [11] Pao-Lung Chen, Ching-Che Chung, Jyh-Neng Yang, and Chen-Yi Lee, “A Clock Generator With Cascaded Dynamic Frequency Counting Loops for Wide Multiplication Range Applications”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 6, JUNE 2006 [12] R. B. Staszewski, D. Leipold, K. Muhammand, and P. T. Balsara, “Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process,” IEEE Trans. Circuit Syst. II, Analog Digit. Signal Process., Vol. 50, no. 11, pp. 815-822, Nov. 2003. [13] P. Raha, S. Randall, R. Jennings, B. Helmick, A. Amerasekera, and B. Haroun, “A robust delay line architecture in a 0.13-um CMOS technology node for reduced design and process sensitivity,” in Proc. ISQED’02, Mar. 2002, pp. 148-153. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26261 | - |
| dc.description.abstract | 本論文使用3um LTPS TFT製程設計一個全數位式鎖相迴路，用來產生倍頻的時脈，本鎖相迴路的輸出頻率範圍是0.625MHz~12MHz，倍頻範圍是1~30倍，模擬結果時間解析度粗調是5.6ns，微調是0.25ns，而量測結果粗調的時間解析度為8ns。鎖相迴路在電路的應用上是一個重要的模組，近年來發展的潮流也是朝全數位化發展。全數位化的好處是電路對製程的變異性不敏感、電路更改製程容易等。 | zh_TW |
| dc.description.abstract | The thesis presents an all-digital phase-locked loop (ADPLL) as a clock generator implemented in 3um LTPS TFT process. The output frequency range of the ADPLL is from 0.625MHz to 12MHz, the multiplication factors of the reference clock are 1 to 30, and the time resolution of the coarse-tuning part of the DCO is 5.6 ns and that of the fine-tuning part is 0.25ns by simulation. The measuring result of the time resolution of course-tuning part is 8ns. PLL is an essential module in many applications, and the trend of development of PLL is toward all-digital realization. The nature of digital circuits has high immunity against process deviation and it is easy for circuits to be ported among different processes. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T07:04:25Z (GMT). No. of bitstreams: 1 ntu-98-R94943089-1.pdf: 3239256 bytes, checksum: e6c7c7ab2684960e9773bdc022c951f5 (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | 中文摘要 I
Abstract II 圖目錄 VI 表目錄 IX 第一章 簡介 1 ________________________________________________________________________________ 1.1 低溫多晶矽薄膜電晶體介紹 1 1.2 全數位式鎖相迴路 2 1.3 動機 2 1.4 論文架構 3 第二章 低溫多晶矽薄膜電晶體 5 ________________________________________________________________________________ 2.1 低溫多晶矽薄膜電晶體介紹 5 2.2 電晶體特性曲線 6 2.3 電路設計考量 9 2.3.1 臨界電壓變異性( ) 9 2.3.2 自發熱效應(self-heating) 10 第三章 鎖相迴路介紹 11 ________________________________________________________________________________ 3.1 類比式鎖相迴路 11 3.2 數位控制式鎖相迴路 13 3.3 全數位式鎖相迴路 14 3.4 鎖相迴路比較 18 第四章 全數位式鎖相迴路架構 19 ________________________________________________________________________________ 4.1 電路架構 19 4.2 頻率及相位鎖定演算法 22 4.3 穩定度分析 23 4.4 頻率鎖定 24 4.5 相位鎖定 26 4.6 電路規格 27 4.7 行為模擬 27 第五章 電路模組設計 31 ________________________________________________________________________________ 5.1 數位控制震盪器 31 5.2 數位式相位頻率偵測器 36 5.3 計數器 37 5.4 正反器 38 5.5 鎖定偵測器 42 5.6 Mask 44 5.7 增益控制器 45 第六章 量測結果及閉迴路模擬 47 ________________________________________________________________________________ 6.1 數位控制震盪器量測結果 47 6.2 全數位式鎖相迴路模擬結果 53 第七章 結論及展望 58 _____________________________________________________________________________________ 7.1 結論 58 7.2 未來展望 59 參考文獻 60 | |
| dc.language.iso | zh-TW | |
| dc.subject | 全數位式鎖相迴路 | zh_TW |
| dc.subject | 低溫多晶矽薄膜電晶體 | zh_TW |
| dc.subject | all-digital phase-locked loop | en |
| dc.subject | LTPS TFT | en |
| dc.title | 以低溫多晶矽薄膜電晶體製程實現之全數位式鎖相迴路設計 | zh_TW |
| dc.title | Design of all-digital phase-locked loop implemented in LTPS TFT process | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 陳建中(Jiann-John Chen),陳伯奇(Poki Chen),黃崇禧(Chorng-Sii Hwang) | |
| dc.subject.keyword | 低溫多晶矽薄膜電晶體,全數位式鎖相迴路, | zh_TW |
| dc.subject.keyword | LTPS TFT,all-digital phase-locked loop, | en |
| dc.relation.page | 61 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2009-01-12 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-98-1.pdf 未授權公開取用 | 3.16 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。