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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/25903完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 郭斯彥 | |
| dc.contributor.author | Hung-Po Wang | en |
| dc.contributor.author | 汪宏柏 | zh_TW |
| dc.date.accessioned | 2021-06-08T06:56:51Z | - |
| dc.date.copyright | 2009-07-27 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-07-21 | |
| dc.identifier.citation | [1] Shivakumar Chonnad, Balachander Needamangalam, “A Layered Approach to Behavioral Modeling of Bus Protocol”, IEEE 2003 page 170-173
[2] LoBue, M.T, “Sureying today’s most popular storage interfaces” Computer Volume 35, Issue 12, Dec, 2002 Page(s):48-55 [3] M. El Shobaki, L. Lindh, “A hardware and software monitor for high-level system-on-chip verification” Quality Electronic Design,2001 International Symposium on 26-28 March 2001 Page(s):56-61 [4] F.Sforza, L. Battu, M. Brunelli, A. Castelnuovo, M. Magnaghi, ”A design for verification methodology”, Quality Electronic Design, International Symposium on, pp.50-55,2001 [5] C-N Liu, I-Ling Chen, Jing-Yang. Kou, “An efficient design-for-verification technique for HDLs” Design Automation Conference, 2001, Asia and South Pacific 30 Jan.-2 Feb. 2001 Page(s):103-108 [6] Zhu. Yunshan, R. Prasad, “Compositional verification: an industrial case study” ASIC, 2003 Page(s):282-285 Vol.1 [7] Adrain Evans, Allen Siburt, Gary Vrckovnik, thane Brown, Mario Dufresne, Geoffery Hall, Tung Ho, Ying Liu, “Functional Verification of Large ASICs” [8] Lukai Cai and Daniel Gajski, “Transaction level modeling: an overview”, Hardware/Software Codesign and System Synthesis, 2003 [9] Mohammed El Shobaki, Lennart Lindh, “A Hardware and software for High-Level System-on-chip Verification”, IEEE 2001 [10] Eugene Zhang and Einat Yogev, “Functional verification with completely self-checking tests” , IEEE International VerilogHDL Conference, April 1997, pp.2-9 [11] Murail Kudlugi, Soha Hassoum, Charles Selvidgr, Duaine Pryor, “A Transaction-Based Unified Simulation/Emulation Architecture for Functional Verification”, DAC Las Vegas Nevada, USA 2001, June page 18-22 [12] Matthias Bauer, Wolfgang Ecker, “Hardware/Software Co-Simulation in a VHDL-based Test Bench Approach”, DAC 1997 [13] Kuang-Chiem Chem, “Assertion-based verification for SoC designs”, ASIC, 2003. Proceedings. 5th International Conference on Volume 1, 21-24 Oct. 2003 Page(s):21-15 Vol.1 [14] 蘇有吉, “Integrating C and Verilog into a Simulation-Based Verification Environment for PCE-X 2.0 Bus” 2003 [15] 尤建智, “System Level Assertion-Based Verification Environment for PCI/PCE-X and PCI-Express” 2004 [16] 鐘智能, “Implementations of Bus Functional Model for the PCI Express System” 2004 [17] 黃鼎鈞, “A Functional Verification Environment for Advanced Switching Architecture” 2004 [18] Universal Serial Bus Specification, Revision 2.0 [19] Enhanced Host Controller Interface (EHCI) Specification for USB, Revision 1.0 [20] Open Host Controller Interface (OHCI) Specification for USB, Revision 1.0a [21] USB 2.0 Universal Transceiver Macrocell Interface (UTMI) Specification, Version 1.05 [22] USB Function IP Core, Reversion 1.5 [23] “DesignWare USB 2 PHY ONE-PORT HARD MACRO for IBM 0.13 um Cu-11 Databook”, Synopsys Corporation [24] “USB 2.0 OHCI/EHCI Host w/OPB Bridge/1 UTMI+ Port Core Databook Revision 1”, IBM Corporation [25] “128-bit Processor Local Bus Architecture Specifications Version 4.6” , IBM Corporation [26] Don Anderson, Dave Dzatko “USB System Architecture” Second Edition, 2001 [27] ICC User Guide Product Version 8.1, Cadence Corporation [28] ICC Analysis User Guide Product Version 8.1, Cadence Corporation | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/25903 | - |
| dc.description.abstract | 隨著單晶片系統的設計複雜度增高，驗證成為整個設計流程的瓶頸。現今的驗證還是依據統模擬。但當系統的複雜度增加，模擬時間的增高將使得模擬的效率大為降低；正確性式晶片設計的主要目標，在特殊用途積體電路(ASIC)的設計中，功能性涵蓋率可以代表系統的正確性。如何有效減少模擬時間和增加系統的功能性涵蓋率，成為今日積體電路設計和驗證工程師所面臨的最大難題。
為了解決上述問題，本篇論文題出了一套USB的匯流排功能性模組(BFM)。在行為層級方面，匯流排功能性模組製定的標準相同。藉著測試電路的行為模式，模擬時間可以有效被控制。本文所設計的功能性模組接式可以被控制多項參數、以及可程式化的。所以我們可應用這些模組來建構USB的驗證環境。我們可以利用這個模組當範本：藉著傳送封包給欲測試的模組，接收測試模組的回傳封包來檢查欲測試模組的正確性。論文最後提出了驗證的環境，期望對於USB晶片設計者，能有更多幫助 | zh_TW |
| dc.description.abstract | Due to the increasing complexity of modern SoC designs, verification has become one of the bottlenecks of the entire IC design process [5]. Current verification strategy, based on traditional hardware simulation, is not able to fulfill designer’s need efficiently because of the escalation simulation time. Functional correctness is the most fundamental requirement for all hardware design. How to reduce the simulation time and increase the functional coverage are the primary issues that designers and researchers need to solve right away.
In this thesis I provide a set of Universal Serial Bus (USB) Bus Functional Models (BFM), congruent to USB specification. By testing design under verification (DUV) in the behavior level, simulation time can be reduced. The BFM are configurable and programmable. We could construct all topologies of the USB system using the BFM. USB BFM can become a golden model, send packets to DUV, and receive packets from DUV to check if it’s functional correctly. Finally we will provide a USB simulation environment using USB BFM for designers to be a reference in chip or ip design . | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T06:56:51Z (GMT). No. of bitstreams: 1 ntu-98-R96943110-1.pdf: 1076734 bytes, checksum: cfdd207452174dcae4a5f4afec8a6016 (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | 中文摘要 i
ABSTRACT ii CONTENTS iii LIST OF FIGURES vi LIST OF TABLES viii Chapter 1 Introduction 1 1.1 Concept of Bus Functional Model 1 1.2 USB Bus Functional Models 2 1.3 Organization of this Thesis 2 Chapter 2 Overview of USB System 4 2.1 Architecture 4 2.2 USB Communications Model 10 2.2.1 Transfers 10 2.2.2 The USB Driver, IRPs, and Frames 11 2.3 Transfer Modes 12 2.3.1 Control Transfer 12 2.3.2 Isochronous Transfer 14 2.3.3 Bulk Transfer 15 2.3.4 Interrupt Transfer 17 2.4 Error Handling 18 2.4.1 Packet Errors 18 2.4.2 Bus Time-Out 23 2.4.3 False EOPs 24 2.4.4 Data Toggle Errors 24 2.4.5 Transfer Error Recovery 24 Chapter 3 USB Bus Functional Model 26 3.1 USB Device Architecture 26 3.1.1 Clocks 26 3.1.2 Host Inrerface 27 3.1.3 Memory Interface and Arbiter 27 3.1.4 Protocol Layer (PL) 28 3.1.5 UTMI I/F 29 3.2 USB Device Operation 30 3.2.1 Endpoints 31 3.2.2 DMA Operation 32 3.2.3 USB Core Memory Size 33 3.2.4 USB Core Behavior 33 3.2.5 USB Core Flowcharts 33 3.2.6 Interrupts 37 3.3 USB Device Registers 38 3.3.1 Endpoint Registers 39 3.3.2 Endpoint Buffer Registers (EP_BUF) 42 Chapter 4 USB Test Environment 44 4.1 Overview 44 4.1.1 Introduction 44 4.1.2 Main Features 44 4.2 Software Interface 45 4.3 Processor Local Bus (PLB) 46 4.3.1 PLB Environment 48 4.3.2 PLB Toolkit Test Bench 48 4.3.3 PLB Bus Functional Compiler 49 4.3.4 PLB Bus Models 50 4.4 USB Host - EHCI & OHCI 51 4.4.1 OHCI 51 4.4.2 EHCI 53 Chapter 5 Verification and Application Results 65 5.1 Introduction to ICC 65 5.2 Verification Result 66 5.2.1 Patterns 66 5.2.2 Code Coverage and FSM Coverage 66 5.3 Application 67 Chapter 6 Conclusion and Future Works 69 6.1 Conclusion 69 6.2 Future Works 69 References 70 Appendix 72 | |
| dc.language.iso | en | |
| dc.title | USB系統之匯流排功能性模組的驗證與實作 | zh_TW |
| dc.title | Verification and Implementation of Bus Functional Models for USB System | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 雷欽隆,袁世一,王思齊,呂學坤 | |
| dc.subject.keyword | 匯流排功能性模組, | zh_TW |
| dc.subject.keyword | Bus Functional Model, | en |
| dc.relation.page | 74 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2009-07-22 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-98-1.pdf 未授權公開取用 | 1.05 MB | Adobe PDF |
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