以延遲線量測週期性抖動之可測試性技術

Abstract

在這篇論文中, 基於週期追蹤, 我們提出一個在晶片上可萃取正弦抖動的技術. 這個技術是可在實現在晶片上的方案. 利用一個可變的延遲線和一個相位比較器去追蹤訊號的週期長度, 卻不需要外加的參考訊號. 我們應用數位信號處理技術來得到訊號週期的序列, 然後求得正弦抖動的振幅和頻率. 另外, 採用數值模擬來確認這個構想, 這些結果表示我們提出的方法不論在振幅或是週期的估計都可以達到高精確度, 而且即使有隨機抖動和延遲線的變異, 這個技術也相當強健.

In this thesis, an on-chip sinusoidal jitter extraction technique based on period tracking is presented. The proposed technique is a viable on-chip solution. It utilizes a variable delay line and a phase comparator to track the signal’s cycle lengths without external reference. Digital signal processing techniques are then applied to the obtained signal period sequence to derive the amplitudes and frequencies of the sinusoidal jitter components. Numerical simulations are performed to validate the idea. The results show that the proposed approach can achieve high amplitude and frequency estimation accuracy and is robust in the presence of random jitter components and delay line variations.