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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃俊郎 | |
| dc.contributor.author | Chia-Yuan Kuo | en |
| dc.contributor.author | 郭嘉元 | zh_TW |
| dc.date.accessioned | 2021-06-08T06:25:17Z | - |
| dc.date.copyright | 2006-07-31 | |
| dc.date.issued | 2006 | |
| dc.date.submitted | 2006-07-28 | |
| dc.identifier.citation | [1] VCOBIST. Credence Systems Corporation.
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Musha, “Timing jitter measurement of 10 Gbps bit clock signals using frequency division,” in Proc. IEEE VLSI Test Symp., 2002, pp. 207–212. [14] Fibre Channel—Methodologies for Jitter Specification, National Committee for Information Technology Standardization (NCITS), T11.2/Project 1316-DT/Rev. 4.0, Nov. 12, 2001. [15] Supplement to Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, IEEE Draft P802.3ae, April 2002. [16] Y. Cai, S. A. Werner, G. J. Zhang, M. J. Olsen, R. D. Brink, “Jitter testing for multi-gigabit backplane SerDes,” in Proc. IEEE Int. Test Conf., 2002, pp. 700-709. [17] M. Shimanouchi, “Periodic jitter injection with direct time synthesis by SPPTM ATE for SerDes jitter tolerance test in production,” in Proc. IEEE Int. Test Conf., 2003, pp. 48-57. [18] Understanding and characterizing timing jitter, Tektronix Technology, Application notes 55W-16146-1, 2003. [19] Fibre Channel—Methodologies for Jitter Specification, National Committee for Information Technology Standardization (NCITS), T11.2/Project 1316-DT/Rev. 14.0, 2004. [20] W. Dalal and D. Rosenthal, “Measuring of high speed data channels using undersampling techniques,” in Proc. IEEE Int. Test Conf., 1998, pp. 819–823. [21] M. Li and et al., “A new method for jitter decomposition through its distribution tail fitting,” in Proc. IEEE Int. Test Conf., 1999, pp. 788–794. [22] S. Jie, M. Li, and J Wilstrup, “A demonstration of deterministic jitter (DJ) deconvolution,” in Proc. IEEE Instrumentation and Measurement Technology Conf., 2002, pp. 293–298. [23] Y. Cai, B. Laquai, and K. Luchman, “Jitter testing for gigabit serial communication transceivers,” in IEEE Design & Test of Computers, vol. 19, pp. 66–74, Jan.–Feb. 2002. [24] Y. Cai, et al., “Jitter testing for multi-gigabit backplane SerDes – techniques to decompose and combine various types of Jitter,” in Proc. IEEE Int. Test Conf., 2002, pp. 700–709. [25] A.L. Lance, W.D. Seal, F.G. Mendoza, N. Hudson, “Phase noise measurements in the frequency domain,” IEEE Int. Microwave Symp. Dig., vol. 77, pp. 110–113, June 1977. [26] D. Adamson, “A possible alternative method of making traceable phase noise measurements,” in IEE Colloquium on Microwave Measurements, 1999, pp. 7/1–7/6. [27] F.L. Walls and A.J.D. Clements, “Extending the range and accuracy of phase noise measurements,” in Proc. of Frequency Control Symp., 1988, pp. 432–441. [28] W.F. Walls, “Cross-correlation phase noise measurements,” in Proc. of Frequency Control Symp., 1992, pp. 257–261. [29] M.M. Driscoll, “Enhanced range phase noise measurements of voltage-controlled phase shifters using carrier nulling,” in Proc. of Frequency Control Symp., 1998, pp. 226–234. [30] J.M. Yang, D.C. Yang, P.G. Cheng and J.M. Dickson, “Automated phase noise measurement of Ku-band MMIC VCO on-wafer,” in Proc. of Int. Microwave Symp. Dig., 1999, pp. 1763–1766. [31] L. Angrisani, M. D'Apuzzo and M. D'Arco, “A digital signal processing approach for phase noise measurement,” IEEE Trans. on Instrumentation and Measurement, vol. 50, pp. 930–935, August 2001. [32] H.S. Nam, B. Cuddy and D. Luecking, “A phase noise spectrum test solution for high volume mixed signal/wireless automatic test equipments,” in Proc. Int. Test Conf., 2001, pp. 957–964. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/25695 | - |
| dc.description.abstract | 在這篇論文中, 基於週期追蹤, 我們提出一個在晶片上可萃取正弦抖動的技術. 這個技術是可在實現在晶片上的方案. 利用一個可變的延遲線和一個相位比較器去追蹤訊號的週期長度, 卻不需要外加的參考訊號. 我們應用數位信號處理技術來得到訊號週期的序列, 然後求得正弦抖動的振幅和頻率. 另外, 採用數值模擬來確認這個構想, 這些結果表示我們提出的方法不論在振幅或是週期的估計都可以達到高精確度, 而且即使有隨機抖動和延遲線的變異, 這個技術也相當強健. | zh_TW |
| dc.description.abstract | In this thesis, an on-chip sinusoidal jitter extraction technique based on period tracking is presented. The proposed technique is a viable on-chip solution. It utilizes a variable delay line and a phase comparator to track the signal’s cycle lengths without external reference. Digital signal processing techniques are then applied to the obtained signal period sequence to derive the amplitudes and frequencies of the sinusoidal jitter components. Numerical simulations are performed to validate the idea. The results show that the proposed approach can achieve high amplitude and frequency estimation accuracy and is robust in the presence of random jitter components and delay line variations. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T06:25:17Z (GMT). No. of bitstreams: 1 ntu-95-R93943001-1.pdf: 986543 bytes, checksum: 89bec305bf8648c3d955f34dc761035b (MD5) Previous issue date: 2006 | en |
| dc.description.tableofcontents | CHAPTER 1 INTRODUCTION 1
1.1 Motivation [19] 1 1.2 Typical SerDes architecture 2 1.3 Review of the previous techniques 3 1.4 The proposed technique 4 1.5 Thesis organization 5 CHAPTER 2 BACKGROUND 6 2.1 Definition of jitter [18] 6 2.2 The jitter model 8 2.2.1 Random jitter 9 2.2.2 Sinusoidal jitter (Periodic jitter) 10 2.2.3 Data-dependent jitter 11 2.2.4 Duty-cycle dependent jitter 12 2.3 Previous techniques 12 2.3.1 Histogram-based methods 12 2.3.2 Phase noise measurement methods [19] 14 2.3.3 The Δ methods 17 2.3.4 The jitter spectral analysis methods 19 CHAPTER 3 THE PROPOSED SJ EXTRACTION TECHNIQUE 21 3.1 Implementation issue 21 3.2 Basic idea 21 3.3 Period comparator 22 3.4 The sinusoidal jitter extraction circuit 23 3.5 The period tracking algorithm 25 3.6 A period tracking example 26 3.7 Post-processing 29 3.7.1 Windowing 31 3.7.2 Spectral peak interpolation 32 3.7.3 Amplitude compensation 33 CHAPTER 4 SIMULATION RESULTS 34 4.1 Simulation setup 34 4.2 Simulation results 35 4.2.1 Impact of N 35 4.2.2 Impact of RJ strength 36 4.2.3 Impact of delay line resolution 37 4.2.4 Impact of SJ frequency 38 4.2.5 Impact of phase difference between two SJ 39 4.2.6 Impact of local process variation 40 4.2.7 Summary of the simulation results 40 CHAPTER 5 CONCLUSION 41 REFERENCE 42 | |
| dc.language.iso | en | |
| dc.subject | 抖動量測 | zh_TW |
| dc.subject | 抖動 | zh_TW |
| dc.subject | 正弦抖動 | zh_TW |
| dc.title | 以延遲線量測週期性抖動之可測試性技術 | zh_TW |
| dc.title | A Delay Line Based Design-for-Test Technique for Sinusoidal Jitter Measurement | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 94-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 呂良鴻,洪浩喬 | |
| dc.subject.keyword | 抖動,正弦抖動,抖動量測, | zh_TW |
| dc.subject.keyword | jitter,sinusoidal jitter,jitter measurement, | en |
| dc.relation.page | 44 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2006-07-29 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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