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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 王勝德 | |
dc.contributor.author | Zhen-Lung Chen | en |
dc.contributor.author | 陳振隆 | zh_TW |
dc.date.accessioned | 2021-06-08T06:02:41Z | - |
dc.date.copyright | 2007-07-30 | |
dc.date.issued | 2007 | |
dc.date.submitted | 2007-07-24 | |
dc.identifier.citation | [1]CoWare, Inc, “http://www.coware.com”
[2]P. Schaumont, and I. Verbauwhede, “a component-based design environment for esl design,” IEEE Design & Test, 2006. [3]SystemC, “http://www.systemc.org/” [4]Kurt Keutzer, Sharad Malik, Richard Newton, Jan Rabaey, and Alberto Sangiovanni-Vincentelli, “System-level design:orthogonalization of concerns and platform-based design,” IEEE Trans. Computer-Aided Design, vol. 19, pp. 1523-1543, Dec. 2000. [5]D. Densmore, R. Passerone, and A. Sangiovanni-Vincentelli, “A Platform-Based Taxonomy for ESL Design,” IEEE Design and Test of Computers, 2006. [6]T. Hollstein, J. Becker, and A. Kirschbaum, HiPART: A New Hierarchical Semi-Interactive HW/SW Partitioning Approach with Fast Debugging for Real-Time Embedded Systems, 6th International Workshop on Hardware/Software Codesign, 1998. [7]Axys Design, “http://www.axysdesign.com” [8]E. D. Lagnese, and D. E. Thomas , “Architectural Partitioning for System Level Design,” Design Automation, 1989. 26th Conference on, 1989. [9]P. Eles, Z. Peng, K. Kuchcinski, and A. Doboli, “System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search,” Design Automation for Embedded Systems, 1997. [10]A. P. Su, and R. Chen, “Applying ESL in A Dual-Core SoC Platform Designing,” International SOC Conference, 2006 IEEE, 2006. [11]V. Reyes, W. Kruijtzer, T. Bautista, G. Alkadi, and A. Nunez, “A unified system-level modeling and simulation environment for MPSoC design: MPEG-4 decoder case study,” Proceedings of the conference on Design, automation and testing Europe: Proceedings, 2006. [12]W. Mueller, A. Rosti, S. Bocchio, E. Riccobene, P. Scandurra, W. Dehaene, and Y. Vanderperren, “UML for ESL Design? Basic Principles, Tools, and Applications,” ICCAD'06, November 5-9, 2006. [13]P. R. Panda , “SystemC-A modeling platform supporting multiple design abstractions,” System Synthesis, 2001. Proceedings. The 14th International Symposium on Volume, Issue, pp. 75-80. 2001. [14]GNU, “http://www.gnu.org/” [15]Microsoft, “http://www.microsoft.com/en/us/default.aspx” [16]Lukai Cai, and Daniel Gajski, “Transaction Level Modeling: An Overview,” Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, October 01-03, 2003. [17]Robert C. Chen, and Alan P. Su, “Construct A PAC PMP SoC Verification Platform Using ESL Design Methodology,” 66. 系統晶片002期, 2006. [18]L. Benini, D. Bertozzi, D. Bruni, N. Drago, F. Fummi, and M. Poncino, “SystemC Co-simulation and Emulation of Multi-Processor SoC Designs,” IEEE Computer, Vol. 36, No. 4, April 2003. [19]M. Caldari, M. Conti, M. Coppola, S. Curaba, L. Pieralisi, and C. Turchetti, “Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0,” Proc. DATE 2003. [20]AMBA, “http://www.arm.com/products/solutions/AMBAHomePage.html” [21]L. Lee, H. Kim, P. Yang, S. Yoo, E.Y. Chung, K.M. Choi, J.T. Kong, and S.K. Eo, “PowerViP: Soc power estimation framework at transaction level ,” Proceedings of the 2006 conference on Asia South Pacific, 2006. [22]M. Caldari, M. Conti, M. Coppola, P. Crippa, S. Orcioni, L .Pieralisi, and C. Turchetti, “System-Level Power Analysis Methodology Applied to the AMBA AHB Bus,” Proc. Design Automation & Test Europe Conference, 2003. [23]T. Lei, Y. Yanhui, and W. Shaojun, “Optimizing SoC Platform Architecture for Multimedia Applications,” ASIC, 2005. ASICON 2005. 6th International Conference On, 2005. [24]O. Ogawa, S. Bayon de Noyer, P. Chauvet, and K. Shinohara, “A practical approach for bus architecture optimization at transaction level,” Proceedings of the conference on Design, Automation and Test, 2003. [25]ADS, “http://www.arm.com/products/DevTools/ADS.html” [26]JPEG-6B, “http://www.ijg.org/” [27]大村正之,深山正幸 原著,溫榮弘 編譯,”C/C++ VLSI設計”, 全華科技圖書股份有限公司,2005. [28]Alan P. Su, Chris Lennard, and Peter Grun, “A Finite State Machine Formalization for Transaction Level Modeling,” Industrial Technology Research Institute, ARM Ltd. [29] PPM Format, “http://www.physics.emory.edu/~weeks/graphics/mkppm.html” | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/25115 | - |
dc.description.abstract | 隨著IC製程的進步,今日已可以將上億個電晶體置入到一個晶片,也使得今日系統晶片的設計日趨複雜。系統層級的設計方法使得系統開發人員可以提高設計的抽象層次,在設計階段能快速的進行實驗,收集數據加以分析與改良系統架構,進而降低系統單晶片開發的複雜度。本篇論文使用了CoWare的系統層級開發工具ConvergenSC,並採用SystemC硬體描述語言。在這篇論文中以交易層級模組化方法設計各個硬體元件建立抽象模型,並使用這些工具在高抽象層次建構三個交易層級的虛擬原型系統架構,藉由模擬出來的數據分析各個系統架構的效能,並加以探討在各個系統架構的優劣點。 | zh_TW |
dc.description.abstract | With the improvement of IC manufacturing technologies, hundred millions of transistors could be put into one chip, and this also leads the system chip design to a more and more complex situation. The design methodology on the system level helps system developers advance the abstraction level of design, validate and verify the design at early stage, collect and analyze data and improve system structures so as to reduce the development complexity of a system-on-chip. The systemC hardware description language and ConvergenSC, a development tool on the system level of CoWare Inc., are adopted in our work. In this thesis, the methodology of transaction-level modeling is used to design hardware components and build abstract models, and the ConvergenSC tool is used to build three transaction-level virtual prototypes of system-on-a-chip platforms. We can analyze the efficiency of each system platform through the simulated data, and evaluate the strength and weakness of system architectures. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T06:02:41Z (GMT). No. of bitstreams: 1 ntu-96-J93921031-1.pdf: 2087695 bytes, checksum: b5e7bbc0e466a8b1c747a1e473a915a1 (MD5) Previous issue date: 2007 | en |
dc.description.tableofcontents | 論文口試委員審定 Ⅰ
志謝 Ⅱ 摘要 Ⅲ ABSTRACT Ⅳ 目錄 Ⅴ 表目錄 Ⅶ 圖目錄 Ⅷ 第一章 序論 1 1.1 研究動機 1 1.2 研究目標 4 1.3 論文架構 4 第二章 相關研究 5 2.1 電子系統層級設計 5 2.2 SystemC 7 2.3 交易層級模組化 12 2.3.1 模組化的技術簡介 13 2.3.2 TLM相關研究討論 15 第三章 方法與實作 17 3.1 問題與想法 17 3.2 軟體方面的實作 17 3.3 硬體方面的實作 20 3.4 架構整合實作 23 3.4.1 ConvergenSC 23 3.4.2 系統平臺的建立 26 第四章 實驗結果分析 30 4.1 實驗說明 30 4.2 系統架構探討 31 4.3 實驗數據 34 4.3.1 匯流排衝突分析 34 4.3.2 效能分析 37 第五章 結論 40 參考文獻 41 | |
dc.language.iso | zh-TW | |
dc.title | 應用系統層級設計方法在SoC平臺架構之探討 | zh_TW |
dc.title | Exploration of SoC Platform Architectures Using the System-Level Design Methodology | en |
dc.type | Thesis | |
dc.date.schoolyear | 95-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 顏嗣鈞,洪士灝 | |
dc.subject.keyword | 系統層級,交易層級模組化,系統單晶片,電子系統級,架構探討, | zh_TW |
dc.subject.keyword | System-level,TLM,SoC,ESL,Architecture Exploration, | en |
dc.relation.page | 43 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2007-07-26 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
顯示於系所單位: | 電機工程學系 |
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