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DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳中平 | |
dc.contributor.author | Bang-Zao Liou | en |
dc.contributor.author | 劉邦灶 | zh_TW |
dc.date.accessioned | 2021-06-08T05:09:35Z | - |
dc.date.copyright | 2011-07-27 | |
dc.date.issued | 2011 | |
dc.date.submitted | 2011-07-22 | |
dc.identifier.citation | [1] Xiang Gao, Eric A. M. Klumperink, Mounir Bohsali, and Bram Nauta, “A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N2 ”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 12, DECEMBER 2009
[2] Y. Ding and K. K. O, “A 21-GHz 8-Modulus prescaler and a 20-GHz phase-locked loop fabricated in 130-nm CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1240–1249, Jun. 2007. [3] R. Gu, A. Yee, Y. Xie, and W. Lee, “A 6.25 GHz 1 V LC-PLL in 0.13-umCMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2006, pp. 594–595. [4] R. Nonis, N. Da Dalt, P. Palestri, and L. Selmi, “Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture,” IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1303–1309, Jun. 2005. [5] X. Gao, E. A. M. Klumperink, P. F. J. Geraedts, and B. Nauta, “Jitter analysis and a benchmarking figure-of-merit for phase-locked loops,” IEEE Trans. Circuits Syst. II, vol. 56, pp. 117–121, Feb. 2009. [6] Chao-Ching Hung, Ding-Shiuan Shen ,and Shen-Iuan Liu,’ A 40GHz Fractional-N Frequency Synthesizer in 0.13μm CMOS’, IEEE Radio Frequency Integrated Circuits Symposium, April 2008. [7] C.-F. Liang, H.-H. Chen, S.-I. Liu, “Spur-Suppression Techniques for Frequency Synthesizers,” IEEE Transactions on Circuits and Systems, Vol. 54, No. 8, March 2007 [8] L. Cho, C. Lee, and S.-I. Liu, “A 1.2-V 37–38.5-GHz eight-phase clock generator in 0.13-umCMOStechnology,” IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1261–1270, Jun. 2007. [9] C.-M. Hsu, M. Z. Straayer, and M. H. Perrott, “A low-noise, wide-BW 3.6 GHz digital ΔΣ fractional-N frequency synthesizer with a noiseshaping time-to-digital converter and quantization noise cancellation,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2776–2786, Dec. 2008. [10] N. Da Dalt, E. Thaller, P. Gregorius, and L. Gazsi, “A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS,” IEEE J. Solid-State Circuits, vol. 40, pp. 1482–1490, Jul. 2005. [11] R. C. H. van de Beek, C. S. Vaucher, D. M. W. Leenaerts, E. A. M. Klumperink, and B. Nauta, “A 2.5–10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-um CMOS,” IEEE J. Solid-State Circuits, vol. 39, pp. 1862–1872, Nov. 2004. [12] T. Lee and A. Hajimiri, “Oscillator phase noise: a tutorial”, JSSC, vol. 35, no.3, pp.326-336, March 2000. [13] B. Razavi, RF Microelectronics, Prentice Hall, 1997. [14] R. B. Watson, Jr. and R. B. Iknaian, “Clock buffer chip with multiple target automatic skewcompensation,” IEEE J. Solid-State Circuits, vol. 30, pp. 1267–1276, Nov. 1995. [15] C. H. Kim et al., “A 64-Mbit, 640-Mbyte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-Mbyte memory system,” IEEE J. Solid-State Circuits, vol. 33, pp. 1703–1710, Nov. 1998. [16] F. M. Gardner, “Charge-pump phase-lock loops,” IEEE Trans. Comm., vol. COM-28, pp. 1849 – 1858, Nov. 1980. [17] T.-C. Lee and W.-L. Lee, “A spur suppression technique for phase-locked frequency synthesizers,” IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 2432-2441, Feb. 2006. [18] J. Lee and Shanghann Wu, “Design and Analysis of a 20-GHz Clock Multiplication Unit in 0.18-μm CMOS Technology,” Digest of Symposium on VLSI Circuits, pp. 140–143, June 2005. [19] B. Razavi, “Monolithic phase-locked loops and clock recovery circuits: theory and design,” IEEE press, 1996. [20] G. Chien, “Low-noise local oscillator design techniques using a DLL based frequency multiplier for wireless applications,” Ph.D. dissertation, Univ. of California, Berkeley, 2000. [21] F. Herzel and B. Razavi, “A Study of Oscillator Jitter Due to Supply and Substrate Noise,” IEEE Trans. Circuits and Systems, Part II, vol. 46, pp. 56–62, Jan. 1999. [22] A. Chandrakasan, W. J. Bowhill, and F. Fox edited “Design of high-performance microprocessor circuit”, p. 240, IEEE press, 2001. [23] G. Chien and P. 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Black, Jr., “A low-jitter skew-calibrated multi-phase clock generator for time-interleaved applications,” International Solid-State Circuits Conference, Feb. 2001, pp. 396–399. [29] J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE Journal of Solid-State Circuits, vol.31, no. 11, pp. 1723–1732, Nov. 1996. [30] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2000 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/23743 | - |
dc.description.abstract | 隨著 CMOS 製程技術的發展和尺寸減小,在不同的應用像高效能類比數位轉換器、有線傳輸、光纖資料傳輸和無線射頻等都需要一個穩定低雜訊的時脈。所以本篇論文將介紹低雜訊鎖相迴路的設計與實作。然而在傳統鎖相回路架構上,雜訊性能沒辦法有卓越的改進。並且充電泵的電流不匹配也造成顯著的靜態相位誤差而造成輸出的時脈抖動。此外由於輸入時脈雜訊造成輸出的時脈誤差放大也降低了系統的效能。本論文中,所推薦的架構之設計考量與實現將被提出。
首先,使用 0.18-μm CMOS 製程的低雜訊鎖相回路架構被提出。此架構基於次取樣鎖相回路以確保有相當程度的雜訊表現。而且因為使用分散式相位偵測器/電流汞降低控制路徑上的由相位偵測器/電流汞電流不匹配所產生的漣波以達到時脈抖動抑制的效果。此外 藉由使用脈衝位置調變(PPM)技術可以更進一步消除周期性的漣波。 | zh_TW |
dc.description.abstract | With the evolution and scaling down of CMOS technologies, a stable clock with low jitter and phase noise is a prerequisite for a variety of applications like high performance analog-to-digital converters, wireline and optical serial data communication links and radio transceivers. Hence, this thesis illustrates the implementation of a low noise phase-locked loop (PLL). However, the noise performance cannot have remarkably improvement constrained by the classical PLL architecture. Besides, the current mismatch of charge pump will result in a significant static phase error. In this thesis, design considerations and realization about the proposed architectures are presented in order to improve the jitter performance.
A 5-GHz low noise Phase-Locked Loop is implemented with 0.18-μm CMOS process is presented. To ensure the low noise of the PLL, this architecture is based on the Sub-Sampling Phase-locked Loop (SSPLL). Moreover, using the distributed PD/CP generated by the divider, the ripple on controlled-line can be lowered and the jitter performance can improve the output jitter generated by PD/CP current mismatch. Besides, the pulse-position modulation (PPM) technique is employed to eliminate the periodic patterns of the ripples on the control-line. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T05:09:35Z (GMT). No. of bitstreams: 1 ntu-100-R96943137-1.pdf: 2013307 bytes, checksum: f8864f0845384e9e91a62a7b47afe745 (MD5) Previous issue date: 2011 | en |
dc.description.tableofcontents | Acknowledgement…………………………………………………………i
Abstract ……………………………………………………………iii Table of Contents…………………………………………………vii List of Figures ……………………………………………………xi List of Tables………………………………………………………xv Chapter 1 Introduction……………………………………………1 1.1 Motivation………………………………………………………1 1.2 Organization of This Thesis……………………………………………………………………2 Chapter 2 Background………………………………………………5 2.1 Basic Concept of Phase-locked Loop…………………………5 2.2 Building Blocks of the PLL……………………………………6 2.2.1 Voltage-Controlled Oscillator (VCO)……………………7 2.2.2 Phase Frequency Detector (PFD) …………………………8 2.2.3 Charge Pump (CP)……………………………………………10 2.2.4 Loop Filter…………………………………………………12 2.2.5 Frequency Divider…………………………………………13 2.3 Basic Analysis of Phase-locked Loop……………………13 2.3.1 Linear Transfer Functions for a simple PLL…………14 2.3.2 Dynamic Behavior Analysis and Loop parameter Design…………………………………………………………………15 2.3.3 Noise Transfer Function of Building Block……………19 2.4 Jitter……………………………………………………………21 Chapter 3 A Low Noise Phase-Locked Loop with Jitter Suppression Technique………………………………………………25 3.1 Introduction……………………………………………………26 3.2 The Proposed PLL Architecture………………………………27 3.2.1 Analysis of Jitter in PLL…………………………………27 3.2.2 Proposed PLL with Sub-sampling PD………………………29 3.2.3 Distributed PD/CP Architecture in the Proposed PLL…31 3.3 Circuit Implementation ………………………………………34 3.3.1 Complementary Voltage-Controlled Oscillator…………34 3.3.2 Sub-sampling Phase Detector and Charge Pump…………35 3.3.3 Pulse-Position Modulation Circuit………………………38 3.3.4 Frequency Divider ……………………………………………39 3.3.5 The Other Building Block …………………………………40 3.4 Simulation Results………………………………………………42 Chapter 4 Experimental Result …………………………………49 4.1 Mistake in the Control Circuit Design ……………………49 4.2 Print Circuit Board Design……………………………………51 4.3 Testing Setup……………………………………………………53 4.4 Experimental Results……………………………………………53 4.5 Summary……………………………………………………………55 Chapter 5 Conclusion ………………………………………………57 Bibliography……………………………………………………………59 | |
dc.language.iso | en | |
dc.title | 使用抑制時脈抖動技術鎖相回路之設計與實作 | zh_TW |
dc.title | Design and Implementation of A Low Noise Phase-Locked Loop with Jitter Suppression Technique | en |
dc.type | Thesis | |
dc.date.schoolyear | 99-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 盧信嘉,盧亦璋 | |
dc.subject.keyword | 鎖相回路,低時脈抖動, | zh_TW |
dc.subject.keyword | PLL,Phase-locked Loop,low jitter, | en |
dc.relation.page | 61 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2011-07-22 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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