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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳良基(Liang-Gee Chen) | |
| dc.contributor.author | Tsung-Chuan Ma | en |
| dc.contributor.author | 馬宗銓 | zh_TW |
| dc.date.accessioned | 2021-06-08T04:59:35Z | - |
| dc.date.copyright | 2010-08-19 | |
| dc.date.issued | 2010 | |
| dc.date.submitted | 2010-08-18 | |
| dc.identifier.citation | [1] R. Q. Quiroga, Z. Nadasdy, and Y. Ben-Shaul, “Unsupervised spike detection and
sorting with wavelets and superparamagnetic clustering,” Neural Comput, vol. 16, pp. 1661–1687, Aug 2004. [2] A.V. Nurmikko, J.P. Donoghue, L.R. Hochberg, W.R. Patterson, Yoon-Kyu Song, C.W. Bull, D.A. Borton, F. Laiwalla, Sunmee Park, Yin Ming, and J. Aceros, “Listening to brain microcircuits for interfacing with external world - progress in wireless implantable microelectronic neuroengineering devices,” Proceedings of the IEEE, vol. 98, no. 3, pp. 375 –388, Mar 2010. [3] R.H.Olsson and K.D. Wise, “A three-dimensioinal neural recording microsystem with implantable data compression circuitry,” . [4] R. R. Harrison and et al., “A low-power integrated circuit for a wireless 100- electrode neural recording system,” IEEE J. Solid State Circuits, vol. 42, no. 1, pp. 123–133, 2007. [5] M. Chae, W. Liu, Z. Yang, T. Chen, J. Kim, M. Sivaprakasam, and M. Yuce, “A 128-channel 6mw wireless neural recording ic with on-the-fly spike sorting and uwb tansmitter,” IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 146–147,603, Mar 2008. [6] E.M. Maynard C.T. Nordhausen and R.A. Normann, “Single unit recording capabilities of a 100-microelectrode array,” Brain Res., pp. 129–140, 1996. [7] Zhi Yang Kimberly Cockerham Wentai Liu Tung-Chien Chen, Kuanfu Chen, “A biomedical multiprocessor soc for closed-loop neuroprosthetic applications,”IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 434–435, 2009. [8] Douglas J. Weber Andrew B. Schwartz, X. Tracy Cui and Daniel W. Moran, “Brain-controlled interfaces: Movement restoration with neural prosthetics,” Neuron, , no. 52, pp. 205–220, Oct. [9] Jozsef Csicsvari Hajime Hirase Kenneth D. Harris, Darrell A. Henze and Gyo, “Accuracy of tetrode spike separation as determined by simultaneous intracellular and extracellular measurements,” . [10] Stephen ODriscoll and Teresa H. Meng, “Adaptive resolution adc array for neural implant,” Engineering in Medicine and Biology Society, pp. 1053 –1056, Sep 2009. [11] T.C.Chen Y.Y.Chen and L.G.Chen, “Accuracy and power tradeoff in spike sorting microsystems with cubic spline interpolation(received),” Proc. IEEE Symp. Circuits. Syst., 2010. [12] V. Karkare, S. Gibson, and D. Markovic, “A 130-uw, 64-channel spike-sorting dsp chip,” Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian, 16-18 2009. [13] L.G.Chen T.C. Chen, W.Liu, “Vlsi architecture of leading eigenvector generation for on-chip principal component analysis spike sorting system,” Engineering in Medicine and Biology Society, pp. 3192–3195, Aug 2008. [14] W.Liu T.C.Chen, K.Chen and L.G.Chen, “On-chip principal component analysis with a mean pre-estimation method for spike sorting,” Proc. IEEE Symp. Circuits. Syst., pp. 3110 –3113, Jun 2009. [15] Wentai Liu Tung-Chien Chen and Liang-Gee Chen, “128-channel spike sorting processor with a parallel-folding structure in 90nm process,” Proc. IEEE Symp. Circuits. Syst., pp. 1253–1256, Jun 2009. [16] T. J. Blanche and N. V. Swindale, “Nyquist interpolation improves neuron yield in multiunit recordings,” J. of Neurosci. Methods, vol. 155, no. 1, pp. 81–91, 2006. [17] M.D. Linderman, G. Santhanam, C.T. Kemere, V. Gilja, S. O’Driscoll, B.M. Yu, A. Afshar, S.I. Ryu, K.V. Shenoy, and T.H. Meng, “Signal processing challenges for neural prostheses,” IEEE Signal Processing Mag., vol. 25, no. 1, pp. 18 –28, Jan. 2008. [18] Y. J. FanW. A. Chaovalitwongse and R. C. Sachdeo, “On the time series k-nearest neighbor classification of abnormal brain activity,” IEEE Trans. on systems, man, and cybernetics. Part A, Systems and humans, vol. 37, no. 6, pp. 1005–1016, 2007. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/23347 | - |
| dc.description.abstract | 本篇論文實現可支援128通道之神經元排序微處理器，並且提出以事件(event)為基礎的系統架構，可滿足神經輔具與神經科學研究之應用。近年歸功於在神經生物學上的研究發展，許多諸如癲癇、帕金森氏症、阿茲海默症等病症皆被證實起因於患者腦部功能喪失或是發生病變。為了連結腦部功能與病症起因，神經生物學者與醫療學者皆致力於人類腦部功能與生理訊號之研究，並且發現人類神經元細胞之間的訊息傳遞得以解釋人類腦部發生病變之原因，因而必須透過硬體將訊號從生物體內處出與並且分析訊號。除了針對神經科學研究的應用，神經輔具亦透過對大腦損傷患者的腦部做訊號分析，得到患者所想要做的動作與指令，進一步控制機械手臂或是對電腦下達指令，以達成跟外界溝通的需求。
針對神經科學及神經輔具之研究應用，必須偵測大量神經元細胞之間的訊號傳遞，並且對傳遞訊號加以分析，如何同時達到降低消耗功率以及硬體面積並且符合可植入硬體的規格，便是硬體設計的關鍵所在。 神經元排序演算法步驟依序為濾波、神經元訊號偵測、內插對齊、特稱取出以及分類。在考慮每個步驟的運算特性與神經訊號在生物體上的異質性，本篇論文將硬體架構分為ASIC(Application Specific Integrated Circuit)與RISC(Reduced Instruction Set Computing)兩部分，其中濾波、內插對齊部分以ASIC方式實現；在神經元訊號偵測、特稱取出以及分類部分，在實際應用上會有多個演算法的需求，因此以RISC方式實現硬體。 從動物及人體實驗的結果顯示，神經元細胞每秒發出訊號頻率約為每秒20~30個，每個神經元訊號的持續時間約為1毫秒，因應如此特殊及鬆散的訊號發生頻率，本篇論文所提出的神經元排序微處理器以神經元發出的事件(event)為基礎，可支援到128通道並且每通道功率消耗為0.6微瓦，同時硬體所需面積為2.0x2.8mm2。 | zh_TW |
| dc.description.provenance | Made available in DSpace on 2021-06-08T04:59:35Z (GMT). No. of bitstreams: 1 ntu-99-R97943116-1.pdf: 5943074 bytes, checksum: 0855da5092c6bb293e6bf019e7a2711c (MD5) Previous issue date: 2010 | en |
| dc.description.tableofcontents | 1 Introduction 1
1.1 Motivation and Application . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Neural Signal Processing System Overview . . . . . . . . . . . . . . . 3 1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Preliminary of Spike Sorting Micro-system 5 2.1 Spike Sorting Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 State-of-art Neural Signal Processing Chip . . . . . . . . . . . . . . . . 5 2.3 Specification and Application Requirements . . . . . . . . . . . . . . . 8 3 Architecture for Implantable Event-based 128-Channel Spike Sorting Processor 11 3.1 Design Challenge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 Problem Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 Proposed System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 Module Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.1 Module Improvement . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.2 IAD Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.4.3 Separating Line Classification . . . . . . . . . . . . . . . . . . 43 4 Implementation Result 47 4.1 Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5 Conclusion 51 | |
| dc.language.iso | en | |
| dc.title | 針對神經義肢與神經科學研究應用之
多通到神經元分類微處理器研究 | zh_TW |
| dc.title | The Study on Multi-channel Spike Sorting Micro-processor for Neuroprosthetic and Neuroscientific Applications | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 98-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 吳安宇(An-Yeu Wu),林啟萬(Chii-Wann Lin),楊家輝(Jar-Ferr Yang) | |
| dc.subject.keyword | 神經元訊號排序, | zh_TW |
| dc.subject.keyword | Spike Sorting Microprocessor,Event-based, | en |
| dc.relation.page | 55 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2010-08-18 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-99-1.pdf 目前未授權公開取用 | 5.8 MB | Adobe PDF |
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