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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹(Hsin-Shu Chen) | |
| dc.contributor.author | Yu-Hsun Liu | en |
| dc.contributor.author | 劉宇珣 | zh_TW |
| dc.date.accessioned | 2021-06-08T04:34:48Z | - |
| dc.date.copyright | 2009-08-20 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-08-18 | |
| dc.identifier.citation | [1]“http://www.bluetooth.com/Bluetooth/”,Bluetooth SIG website
[2]Bo Xia, Valdes-Garcia, Edgar Sanchez-Sinencio “A 10-bit 44-MS/s 20-mW Configurable Time-Interleaved Pipeline ADC for a Dual-Mode 802.11b/Bluetooth Receiver” IEEE J. of Solid-State Circuits Vol.41 pp.530-540, March 2006. [3]B.Razavi, Principles of Data Conversion System Design. Wiley-IEEE Press, 1995. [4]Rudy van de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters. Kluwer Academic Publishers, 2003. [5]Mikael Gustavsson, J. Jacob Wikner and N. Nick Tan, CMOS Data Converters for Communications. Kluwer Academic Publishers. [6]S. H. Lewis, H. S. Fetterman, G. F. Gross Jr., R. Ramachandran, and T. R. Viswanathan, “A 10-b 20-Msample/s analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 27, pp. 351-358, Mar. 1992. [7]Chien-Kai Hung, Jian-Feng Shiu, I-Ching Chen and Hsin-Shu Chen “A 6-bit 1.6GS/s Flash ADC in 0.18-um CMOS with Reversed-Reference Dummy” IEEE Solid-State Circuits Conference, 2006 ASSCC, pages:335-338, Nov. 2006. [8]K. Kusumoto, K. Murata, A. Matsuzawa, S. Tada, M. Maruyama, K. Oka, and H.Konishi, “A 10b 20MHz 30mW Pipelined Interpolating CMOS ADC,” IEEE International Solid-State Circuits Conference, pp. 62-63, Feb. 1993. [9]Pedro M. Figueiredo, Paulo Cardoso, Ana Lopes, Carlos Fachada, Naoyuki Hamanishi, Ken Tanabe and Joao Vital “A 90nm CMOS 1.2V 6b 1GS/s Two-Step Subranging ADC” Digest of Technical Papers. ISSCC 2006 IEEE International Pages:568-673 [10]M. Flynn and D. Allstot, “CMOS Folding A/D Converters with Current-Mode Interpolation,” IEEE J. Solid-State Circuits, vol.31, pp. 1248-1255, Sep. 1996. [11]Govert Geelen and Edward Paulus “An 8b 600MS/s 200mW CMOS Folding A/D Converter Using an Amplifier Technique” IEEE International Solid-State Circuits Conference, pp. 254-526, Feb. 2004. [12]Ahmed A. Emira, Alberto Valdes-Garcia, Bo Xia, Ahmed N. Mohieldin Ari Valero-Lopez, Sung T. Moon, Chunyu Xin, Edgar Sanchez-Sinencio “A Dual-Mode 802.11b/Bluetooth Receiver in 0.25um BiCMOS” ISSCC Dig. Tech. Papers, pp.270-271, Feb. 2004. [13]Naveen Verma, Anantha Chandrakasan “A 25uW 100KS/s 12b ADC for Wireless Micro-Sensor Applications” ISSCC Dig. Tech. Papers, pp. 222-224, Feb. 2006 [14]You-Kuang Chang, Chao-Shiun Wang and Chorng-Kuang Wang “A 8-bit 500-KS/s Low Power SAR ADC for Bio-Medical Application” A-SSCC, pp.228-231, Nov. 2007. [15]M. v. Elzakker, E. V. Tuijl, P. Geraedts, D. Schinkel, E. Klumperink and B. Nauta “ A 1.9uW 4.4fJ/Conversion-step 10b 1MS/s Charge Redistribution ADC” ISSCC Dig. Tech. Papers, pp. 244-245, Feb. 2008. [16]Jan Craninckx, Geert Van der Plas “A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS” ISSCC Dig. Tech. Papers, pp. 246-248, Feb. 2007. [17]Vito Giannini, Pierluigi Nuzzo, Vincenzo Chironi, Andrea Baschirotto, Geert Van der Plas, and Jan Craninckx “An 820uW 9b 40MS/s Noise-Tolerant Dynamic SAR ADC in 90nm Digital CMOS”. ISSCC Dig. Tech Papers. pp. 238-240, 2008. [18]Franz Kuttner, “A 1.2V 10b 20MSamples/s Non-Binary Successive Approximation ADC in 0.13um CMOS” ISSCC Dig. Tech Papers. pp. 176-177, 2002. [19]M. Hesener, T.Eichler, A. Hanneberg, D. Herbison, F. Kuttner, and H. Wenske “A 14b 40MS/s Redundant SAR ADC with 480MHz Clock in 0.13um CMOS” ISSCC Dig. Tech. Papers, pp. 249-251, Feb. 2007. [20]Ayaskant Shrivastava “12-bit non-calibrating noise-immune redundant SAR ADC for System-on-a-Chip” ISCAS , pp. 1515-1518, 2006. [21]Gilbert Promitzer “12-bit Low-Power Fully Differential Switched Capacitor Noncalibrating Successive Approximation ADC with 1MS/s”, IEEE J. of Solid-State Circuits, Vol.36, NO.7, July. 2001. [22]P. Confalonieri, M. Zamprogno, F. Girardi. G. Nicollini, and A. Nagari “A 2.7mW 1MSps 10b Analog-to-Digital Converter with Built-in Reference Buffer and 1LSB Accuracy Programmable Input Ranges” Proc. ESSCIRC. pp. 255-258, Sept.2004. [23]Byung-Moo Min; Kim, P.; Bowman, F.W., III; Boisvert, D.M.; Aude, A.J.;”A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC” Solid-State Circuits, IEEE Journal of Volume 38, Issue 12, Dec 2003 Page(s):2031 – 2039 [24]J. Doernberg, H. Lee, and D. A. Hodges, “Full-speed testing of A/D converters,” IEEE J. Solid-State Circuits, vol. 19, No. 6, pp. 820-827, Dec. 1984. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/22948 | - |
| dc.description.abstract | 隨著科技的進步，無線通訊產品也益發的普及到我們日常生活中。在各式無線通訊系統中，藍芽系統更是在其中扮演重要的角色。又因為可攜帶式電子產品的要求，低功率消耗成為設計類比數位轉換器時的必要考量。本論文依據傳統的循序漸近式架構(Successive-Approximation Register)，融合子範圍(Sub-range)的概念。在前面比較裡降低對準確度的要求，進而提升比較速度。再利用重疊動作(Overlap action)把之前比錯的地方校正回來。實現一個12位元的解析度與一千萬赫茲的轉換速度的低功率循序漸進式類比數位轉換器(Successive-Approximation Analog-to-Digital Converter)，來應用在藍芽系統(Bluetooth System)中。本設計採用台積電0.13微米1P8M的製程，晶片操作在10MS/s的取樣頻率，奈奎斯特輸入訊號頻率下，SNDR為59.7dB，SFDR為69.8dB，核心電路功率消耗為3mW。晶片總面積為1.19mm2，核心電路部分約為0.096mm2。 | zh_TW |
| dc.description.abstract | As a result of rapidly improve in the technology, wireless communication devices become more popular in our daily life. Among various wireless communication systems, Bluetooth system plays an important role in that. Because of requirement of portable electrical products, power consumption becomes an essential criterion in the design of Analog-to-Digital Converter (ADC). This thesis presents a method combine traditional Successive-Approximation architecture with Sub-range concept. By this way, we can relieve accuracy requirement on the MSB array and heaving total conversion rate. Then we use overlap action to correct error exist in the MSB comparison. A 12-bit 10MS/s low power consumption Successive-Approximation Analog-to-Digital Converter applied for the Bluetooth system is proposed. This design adopted TSMC 0.13-um 1P8M CMOS process. While the chip operates at sampling rate 10MS/s and Nyquist rate input frequency, the SNDR and SFDR achieve 59.7dB and 69.8dB respectively. The power consumption of core circuit is 3mW. The chip with pads occupies 1.19mm2 and the core area is about 0.096 mm2. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T04:34:48Z (GMT). No. of bitstreams: 1 ntu-98-R95943112-1.pdf: 3496062 bytes, checksum: 4135805116dd98fdde8a4646178bddf7 (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | 致謝................................................................................................................I
摘要...............................................................................................................II Abstract.....................................................................................................III Table of Contents......................................................................................IV List of Figures...........................................................................................VI List of Tables..........................................................................................VIII Chapter 1 Preface.......................................................................................................1 1.1 Introduction to Bluetooth.........................................................................................1 1.2 Motivation...............................................................................................................3 1.3 Thesis Organization.................................................................................................4 Chapter 2 Fundamentals of A/D converter...............................................5 2.1 Introduction.............................................................................................................5 2.2 Performance metrics................................................................................................5 2.2.1 Differential Nonlinearity (DNL)......................................................................5 2.2.2 Integral Nonlinearity (INL)..............................................................................6 2.2.3 Offset Error.......................................................................................................7 2.2.4 Gain Error.........................................................................................................7 2.2.5 Signal-to-Noise ratio (SNR).............................................................................8 2.2.6 Total Harmonic Distortion (THD)....................................................................8 2.2.7 Spurious-Free Dynamic Range (SFDR)...........................................................9 2.2.8 Signal-to-Noise and Distortion Ratio (SNDR).................................................9 2.2.9 Effective Number of Bits (ENOB)...................................................................9 2.3 General architectures of A/D converter.................................................................10 2.3.1 Pipeline A/D converter...................................................................................11 2.3.2 Full flash A/D converter.................................................................................13 2.3.3 Two-step A/D converter.................................................................................14 2.3.4 Folding and interpolating A/D converter........................................................15 2.3.5 Successive-approximation A/D converter......................................................18 2.3.6 Delta-sigma A/D converter.............................................................................20 2.4 Summary...............................................................................................................21 Chapter 3 Design and implementation of this Sub-range SAR ADC...23 3.1 Introduction...........................................................................................................23 3.2 Proposed architecture to increase speed at high resolution...................................25 3.3High-level system design........................................................................................27 3.4 System simulation .................................................................................................29 3.5 Integrated circuit design........................................................................................32 3.5.1 Sub-range capacitor array...............................................................................32 3.5.1.1 Binary search algorithm with the Sub-range concept..............................34 3.5.2 Pre-amplifier...................................................................................................37 3.5.3 Latch-type comparator....................................................................................38 3.5.4 Overlapping logic in the digital controller......................................................40 3.6 Simulation results..................................................................................................43 3.6.1 AC analysis.....................................................................................................43 3.6.2 Transient analysis............................................................................................44 3.6.3 FFT simulation................................................................................................47 3.6.4 Summary.........................................................................................................48 Chapter 4 Test setup and measurement results......................................49 4.1 Introduction...........................................................................................................49 4.2 Floor plan and layout considerations.....................................................................49 4.3 Test environmental setup.......................................................................................51 4.4 PCB design............................................................................................................54 4.5 Experiment results.................................................................................................59 4.5.1 Static performance..........................................................................................61 4.5.2 Dynamic performance....................................................................................63 4.6 Reason of the resolution-degradation....................................................................65 4.7 Summary................................................................................................................67 Chapter 5 Conclusions..............................................................................69 5.1 Conclusions............................................................................................................69 Bibliography...............................................................................................70 Appendix....................................................................................................73 | |
| dc.language.iso | en | |
| dc.subject | 循序漸進式類比數位轉換器 | zh_TW |
| dc.subject | 子範圍 | zh_TW |
| dc.subject | Sub-range | en |
| dc.subject | SAR ADC | en |
| dc.title | 一個低功率子範圍循序漸進式類比數位轉換器 | zh_TW |
| dc.title | A Low Power Sub-range Successive-Approximation ADC | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),顧孟愷(Mong-Kai Ku),蔡宗亨(Tsung-Heng Tsai) | |
| dc.subject.keyword | 循序漸進式類比數位轉換器,子範圍, | zh_TW |
| dc.subject.keyword | SAR ADC,Sub-range, | en |
| dc.relation.page | 79 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2009-08-19 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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