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Title: | BNSyn:針對行為描述階層電路設計之高速合成工具 BNSyn: A Quick Behavioral-Level Synthesis Tool |
Authors: | Chang-Hong Hsu 徐常紘 |
Advisor: | 黃鐘揚(Chung-Yang Huang) |
Keyword: | SystemC,行為階層合成,排程,數學規劃法,控制結構最佳化, SystemC,behavioral synthesis,scheduling,mathematical programming,control optimization, |
Publication Year : | 2011 |
Degree: | 碩士 |
Abstract: | 由於電路複雜度日益增加,傳統使用暫存器移轉階層語言進行設計之流程已經漸漸不符合市場對於效率的需求,現代電路設計已經漸漸轉向系統層級。其中,SystemC由於其強大快速的優點以及與C++語言的相似性,已經是此一層級電路設計所使用的主流語言之一;而SystemC最主要的特性,就是其高度抽象化的能力,此能力使其能夠有效率的詮釋IP的功能以及行為;也因此,SystemC目前被廣泛運用在IP的行為階層設計之上。但現今對於此一語言之合成研究仍然有許多不足或尚未成熟之處,導致直接由SystemC進行合成的設計流程仍不盛行。
在這篇論文中,我們將會介紹我們針對SystemC硬體描述語言的行為階層合成所設計的高速合成工具。此合成工具主要是以延伸斐式網路以及控制-資料相依圖為基礎,以一個高效的正規排程器為核心,在其上建構了一個設計合成以及控制結構最佳化的流程。由於排程器所使用的架構是以數學規劃法中的一個特殊型式的矩陣為主體,且具有此特性之系統能在多項式時間之內得到最佳的整數解,因此本排程器相當適合拿來當作進行行為階層合成以及分析的重要引擎。 而此工具雖針對SystemC所設計,但並不限於SystemC,亦可以應用至其他多種行為階層描述語言。此外,由於本工具的大體架構頗為完整,所以更為之後針對行為階層研究甚至更高抽象層級的研究提供了一個良好的立足點。 As design complexity grows rapidly, conventional RT-level design flow is unsatisfactory to the even-quicker time-to-market requirements. The modern trend of the circuit design is now turning to the Electronic-System-Level (ESL) flow. Among various kinds of system-level description languages, SystemC, due to its powerfulness and efficiency, and the similarity to the well-known C++ language, has already become one of the major design languages in such a level. Moreover, SystemC’s major characteristic, which is its outstanding efficacy of abstraction, leads to the language’s great capability of efficiently modeling IP behaviors and functions; therefore, nowadays, SystemC is prevailing in the realm of behavioral-level IP design. Nevertheless, because of the synthesis tools’ immaturity, it is still not well-accepted for the designers to apply direct synthesis on the circuits written in SystemC in the design flow. In this thesis, we introduce the proposed SystemC behavioral synthesis tool. This tool utilizes our extended Petri Net model and the proposed control-data dependency graph as the language interpreting representations, a highly efficient formal scheduler as its solving kernel, and an integrated flow for design synthesis and control optimization. Since this formal scheduler uses a special form in mathematical programming, it is capable of obtaining optimal integral solutions in polynomial time. Such a characteristic makes the scheduler suitable for coping with many behavioral researches and analyses. Although this tool is designed for SystemC language, it does not limit itself to SystemC; given a proper frontend, the kernel can be applied to many other high-level description languages. Lastly, because of the complete framework, this tool provides a good entry point for further researches in behavioral or higher levels of abstraction. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/22798 |
Fulltext Rights: | 未授權 |
Appears in Collections: | 電機工程學系 |
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ntu-100-1.pdf Restricted Access | 4.13 MB | Adobe PDF |
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