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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃鐘揚(Chung-Yang Huang) | |
| dc.contributor.author | Chang-Hong Hsu | en |
| dc.contributor.author | 徐常紘 | zh_TW |
| dc.date.accessioned | 2021-06-08T04:28:36Z | - |
| dc.date.copyright | 2011-08-22 | |
| dc.date.issued | 2011 | |
| dc.date.submitted | 2011-08-16 | |
| dc.identifier.citation | [1] M. He, M. C. Tsai, X. Wu, F. Wang, and R. Nasr, “Hardware/Software Codesign Pedagogy for the Industry,” 2008, pp. 279-284.
[2] “Open SystemC Initiative.” [Online]. Available: http://www.systemc.org/. [3] “SpecC.” [Online]. Available: http://www.cecs.uci.edu/~specc/. [4] Arvind, “Bluespec: A language for hardware design, simulation, synthesis and verification Invited Talk,” in Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. [5] D. D. Gajski, N. D. Dutt, A. C.-H. Wu, and S. Y.-L. Lin, High-level Synthesis: Introduction to Chip and System Design. Kiuwer Academic Publishers, 1992. [6] M. C. McFarland, A. C. Parker, and R. Camposano, “The high-level synthesis of digital systems,” Proceedings of the IEEE, vol. 78, no. 2, IEEE, pp. 301–318, 1990. [7] Y.-L. Lin, “Recent Developments in High-Level Synthesis,” ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 2, no. 1, pp. 2-21, 1997. [8] C.-N. Chou, C.-H. Hsu, Y.-T. Chao, and C.-Y. (Ric) Huang, “Formal Deadlock Checking on High-Level SystemC Designs,” in International Conference on Computer-Aided Design (ICCAD), 2010. [9] S.-J. Cai, “Deadlock Checking of SystemC Designs Using Extended Petri-Net Model,” National Taiwan University, 2009. [10] J. Cong and Z. Zhang, “An efficient and versatile scheduling algorithm based on SDC formulation,” in 2006 43rd ACM/IEEE Design Automation Conference, 2006, pp. 433-438. [11] J. Cong, B. Liu, and Z. Zhang, “Scheduling with soft constraints,” in Proceedings of the 2009 International Conference on Computer-Aided Design - ICCAD ’09, 2009, pp. 47-54. [12] R. Jain, A. Mujumdar, A. Sharma, and H. Wang, “Empirical evaluation of some high-level synthesis scheduling heuristics,” Proceedings of the 28th conference on ACM/IEEE design automation conference - DAC ’91, pp. 686-689, 1991. [13] E. Musoll and J. Cortadella, “Scheduling and resource binding for low power,” in Proceedings of the 8th international symposium on System synthesis, 1995, pp. 104–109. [14] T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein, Introduction to Algorithms, 2nd ed. The MIT Press, 2001, pp. 601-607. [15] G. Ramalingam, J. Song, L. Joscovicz, and R. E. Miller, “Solving Difference Constraints Incrementally,” Algorithmica, vol. 23, pp. 261-275, 1999. [16] C. H. Papadimitriou and K. Steiglitz, Combinatorial Optimization: Algorithm and Complexity. Dover Publications, Inc., 1998, pp. 316-318. [17] M. Raghavachari, “A constructive method to recognize the total unimodularity of a matrix,” Mathematical Methods of Operations Research, vol. 20, no. 1, pp. 59-61, Jan. 1976. [18] D. S. Hochbaum and J. G. Shanthikumar, “Convex separable optimization is not much harder than linear optimization,” J. ACM, vol. 37, pp. 843-862, 1990. [19] L. Zhong and N. K. Jha, “Interconnect-aware high-level synthesis for low power,” in Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, 2002, p. 117. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/22798 | - |
| dc.description.abstract | 由於電路複雜度日益增加，傳統使用暫存器移轉階層語言進行設計之流程已經漸漸不符合市場對於效率的需求，現代電路設計已經漸漸轉向系統層級。其中，SystemC由於其強大快速的優點以及與C++語言的相似性，已經是此一層級電路設計所使用的主流語言之一；而SystemC最主要的特性，就是其高度抽象化的能力，此能力使其能夠有效率的詮釋IP的功能以及行為；也因此，SystemC目前被廣泛運用在IP的行為階層設計之上。但現今對於此一語言之合成研究仍然有許多不足或尚未成熟之處，導致直接由SystemC進行合成的設計流程仍不盛行。
在這篇論文中，我們將會介紹我們針對SystemC硬體描述語言的行為階層合成所設計的高速合成工具。此合成工具主要是以延伸斐式網路以及控制-資料相依圖為基礎，以一個高效的正規排程器為核心，在其上建構了一個設計合成以及控制結構最佳化的流程。由於排程器所使用的架構是以數學規劃法中的一個特殊型式的矩陣為主體，且具有此特性之系統能在多項式時間之內得到最佳的整數解，因此本排程器相當適合拿來當作進行行為階層合成以及分析的重要引擎。 而此工具雖針對SystemC所設計，但並不限於SystemC，亦可以應用至其他多種行為階層描述語言。此外，由於本工具的大體架構頗為完整，所以更為之後針對行為階層研究甚至更高抽象層級的研究提供了一個良好的立足點。 | zh_TW |
| dc.description.abstract | As design complexity grows rapidly, conventional RT-level design flow is unsatisfactory to the even-quicker time-to-market requirements. The modern trend of the circuit design is now turning to the Electronic-System-Level (ESL) flow. Among various kinds of system-level description languages, SystemC, due to its powerfulness and efficiency, and the similarity to the well-known C++ language, has already become one of the major design languages in such a level. Moreover, SystemC’s major characteristic, which is its outstanding efficacy of abstraction, leads to the language’s great capability of efficiently modeling IP behaviors and functions; therefore, nowadays, SystemC is prevailing in the realm of behavioral-level IP design. Nevertheless, because of the synthesis tools’ immaturity, it is still not well-accepted for the designers to apply direct synthesis on the circuits written in SystemC in the design flow.
In this thesis, we introduce the proposed SystemC behavioral synthesis tool. This tool utilizes our extended Petri Net model and the proposed control-data dependency graph as the language interpreting representations, a highly efficient formal scheduler as its solving kernel, and an integrated flow for design synthesis and control optimization. Since this formal scheduler uses a special form in mathematical programming, it is capable of obtaining optimal integral solutions in polynomial time. Such a characteristic makes the scheduler suitable for coping with many behavioral researches and analyses. Although this tool is designed for SystemC language, it does not limit itself to SystemC; given a proper frontend, the kernel can be applied to many other high-level description languages. Lastly, because of the complete framework, this tool provides a good entry point for further researches in behavioral or higher levels of abstraction. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T04:28:36Z (GMT). No. of bitstreams: 1 ntu-100-R97921023-1.pdf: 4232251 bytes, checksum: f3a98bd590cba326252bfefa63c1fa7b (MD5) Previous issue date: 2011 | en |
| dc.description.tableofcontents | 口試委員會審定書 #
誌謝 i 中文摘要 iv ABSTRACT v CONTENTS vii LIST OF FIGURES xi LIST OF TABLES xiii LIST OF ALGORITHMS xiv Chapter 1 Introduction 1 1.1 Introduction to Electronic System Level Design 1 1.2 The Basic Concept of Synthesis 2 1.3 Why Behavioral Synthesis? 4 1.4 Objective of the Thesis 4 1.5 The Organization of the Thesis 5 Chapter 2 Preliminaries 7 2.1 Behavioral Synthesis 7 2.1.1 Control and Data Separation 7 2.1.2 Tasks in Behavioral Synthesis 8 2.2 The Basic Concept of Petri Net 10 2.2.1 Basic Definitions 10 2.2.2 Execution Rules 13 2.3 The Introduction of Control/Data Flow Graph 14 Chapter 3 Overall Framework and Design Modeling 16 3.1 The Overall Flow 16 3.2 The Proposed Extended Petri Net Model 17 3.2.1 Control Transition 18 3.2.2 Operator Transition 19 3.2.3 Branch Transition 19 3.3 Modeling C++/SystemC Constructs with Extended Petri Net Model 20 3.3.1 Variables 20 3.3.2 Expression Statements 20 3.3.3 Conditional Expressions 22 3.3.4 Control Flow Statements 23 3.3.5 Processes 25 3.3.6 Wait Statement 26 3.3.7 Other C++/SystemC Constructs 28 3.4 Design Interpretation Using Control/Data Dependency Graph 30 3.4.1 Description 30 3.4.2 CDDG Construction 35 3.4.3 Applying Control Relaxation with CDDG 36 Chapter 4 State-Transition Graph Construction 39 4.1 Observations about Synthesis with CDDG Only 39 4.2 The Necessity of Control-Flow View of the Design 41 4.2.1 CFG Description 42 4.2.2 CFG Construction 43 4.3 State-Transition Graph of Synthesized Design 43 4.4 Overall State-Transition Graph Generation Procedure 44 4.5 Proposed Control-Relaxation Technique using CDDG and CFG 46 Chapter 5 Behavioral-Synthesis Kernel 49 5.1 Overview 49 5.2 Scheduling Problem Formulation 50 5.3 Scheduling Variables 51 5.4 Scheduling Constraints 52 5.4.1 Dependency Constraints 53 5.4.2 Timing Constraints 55 5.4.3 Resource Constraints 58 5.5 System of Difference Constraints and Total Unimodularity 61 5.5.1 System of Difference Constraints 61 5.5.2 Total Unimodularity 62 5.6 Linear Objective Functions 63 5.6.1 ASAP and ALAP Scheduling 63 5.6.2 Longest Path Latency Optimization and State Minimization 64 5.7 SDC Formulation’s Capability of Cooperating with Soft Constraints and Convex Objective Functions 65 5.7.1 Soft Constraint and Penalty Method 65 5.7.2 The Validity of Total Unimodularity 67 5.7.3 The Capability of Optimization with Convex Objective Function 68 5.8 Complexity Analysis 69 5.8.1 Number of Variables 69 5.8.2 Number of Constraints 70 5.9 Resource Binding For Low Power 71 5.9.1 Neighborhood Crowdedness 71 5.9.2 Operand Reutilization 72 5.9.3 Binding Heuristic 73 Chapter 6 Experimental Results 74 6.1 Experiment Setups and Environments 74 6.2 Case Study 75 Chapter 7 Conclusions and Future Works 81 Appendix: Web Interface of BNSyn 83 REFERENCE 87 | |
| dc.language.iso | en | |
| dc.subject | 控制結構最佳化 | zh_TW |
| dc.subject | SystemC | zh_TW |
| dc.subject | 行為階層合成 | zh_TW |
| dc.subject | 排程 | zh_TW |
| dc.subject | 數學規劃法 | zh_TW |
| dc.subject | mathematical programming | en |
| dc.subject | control optimization | en |
| dc.subject | SystemC | en |
| dc.subject | behavioral synthesis | en |
| dc.subject | scheduling | en |
| dc.title | BNSyn：針對行為描述階層電路設計之高速合成工具 | zh_TW |
| dc.title | BNSyn: A Quick Behavioral-Level Synthesis Tool | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 99-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 蘇培陞,黃俊達 | |
| dc.subject.keyword | SystemC,行為階層合成,排程,數學規劃法,控制結構最佳化, | zh_TW |
| dc.subject.keyword | SystemC,behavioral synthesis,scheduling,mathematical programming,control optimization, | en |
| dc.relation.page | 88 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2011-08-17 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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| ntu-100-1.pdf 未授權公開取用 | 4.13 MB | Adobe PDF |
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