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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 黃俊郎(Jiun-Lang Huang) | |
dc.contributor.author | Teng-Han Wang | en |
dc.contributor.author | 王騰漢 | zh_TW |
dc.date.accessioned | 2021-06-08T04:18:11Z | - |
dc.date.copyright | 2010-07-29 | |
dc.date.issued | 2010 | |
dc.date.submitted | 2010-07-27 | |
dc.identifier.citation | [1] Fan Wang and Vishwani D. Agrawal, “Single Event Upset: An Embedded Tutorial,” in 21st International Conference on VLSI Design, January, 2008, pp. 429-434.
[2] P. Shivakumar, M. Kistler, S.W. Keckler, D.C. Burger, and L. Alvisi, “Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic,” in 2002 International Conference on Dependable Systems and Networks (DSN), June, 2002, pp. 389-398. [3] Sheng Weiguang, Xiao Liyi, and Mao Zhigang, “Fast soft error rate computing technique based on state probability propagating,” in 4th IEEE Conference on Industrial Electronics and Applications (ICIEA), May 2009, pp. 734-738. [4] “Effects of Neutrons on Programmable Logic: White Paper,” Technical report, Actel Corporation, Dec 2002. [5] M. Omana, G. Papasso, D. Rossi, and C. Metra, “A Model for Transient Fault Propagation in Combinatorial Logic,” in Proc.9th IEEE On-Line Testing Symposium, 2003, pp. 111-115. [6] Peter Hazucha and Christer Svensson, “Impact of CMOS Technology Scaling on the Atmospheric Neutron Soft Error Rate,” in IEEE Transactions on Nuclear Science, Vol. 47, No. 6, Dec, 2000, pp. 2586-2594. [7] Fred L. Yang and Resve A. Saleh, “Simulation and Analysis of Transient Faults in Digital Circuits,” in IEEE J. Solid State Circuits, vol. 27, no.3, March 1992, pp. 258-264. [8] G. C. Messenger, “Collection of Charge on Junction Nodes from Ion Tracks,” in IEEE Transactions on Nuclear Science, vol. 29, no. 6, 1982, pp.2024-2031. [9] J. E. Stine, I. Castellanos, M. Wood, J. Henson, F. Love, W. R. Davis, P. D. Franzon, M. Bucher, S. Basavarajaiah, J. Oh, and R. Jenkal, “FreePDK: An open-source variation-aware design kit”, in IEEE International Conference on Microelectronic Systems Education (MSE), June 2007, pp.173-174. [10] Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, and Adit D. Singh, “Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance”, in IEEE Transactions on VLSI Systems, vol. 15, no. 5, May 2006, pp. 514-524. [11] M. Zhang and N.R. Shanbhag, “A soft error rate analysis (SERA) methodology,' in IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2004, pp. 111-118. [12] Kartik Mohanram, 'Closed-Form Simulation and Robustness Models for SEU-Tolerant Design,' in 23rd IEEE VLSI Test Symposium (VTS), 2005, pp. 327-333. [13] V. Carreno, G. Choi, and R. K. Iyer, “Analog-digital simulation of transient-induced logic errors and upset susceptibility of an advanced control system,” in NASA Technical Memo 4241, 1990. [14] Rajeev R. Rao, Kaviraj Chopra, David Blaauw, and Dennis Sylvester, “An efficient static algorithm for computing the soft error rates of combinational circuits,” in Design, Automation, and Test in Europe (DATE), March 2006, pp. 164-169. [15] G. Asadi and M. B. Tahoori, “An Analytical Approach for Soft Error Rate Estimation in Digital Circuits,” in Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2005, pp. 2991-2994. [16] N. Miskov-Zivanov, D. Marculescu, “Soft Error Rate Analysis for Sequential Circuits,” in Proc. IEEE Design, Automation and Test in Europe (DATE), Apr. 2007, pp. 1436-1441. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/22455 | - |
dc.description.abstract | 由宇宙射線所引起的軟性錯誤,會在奈米層級的超大型積體電路設計上導致嚴重的可靠性問題。如果我們要發展相關的軟性錯誤容錯技術,首先我們必須先分析軟性錯誤在系統階級影響的效應。在這篇論文中,我們在元件庫特徵化的基礎上,提出一個依據於樣本的軟性錯誤率計算方法來計算組合電路和序向電路。我們發展了一個動態的軟性錯誤率模擬器。我們使用 ISCAS'89和ITC'99中的基準電路來比較我們提出的方法與使用HSpice模擬的差異性。我們所提出的方法比使用HSpice模擬快了5 ~ 6個數量級,而誤差只在3%以內。 | zh_TW |
dc.description.abstract | Soft errors due to cosmic rays cause an important reliability problem for nano-scale VLSI designs. If we want to develop the related soft error tolerant techniques, first we need to analyze the effect of soft errors at the system level. In this thesis, we propose a pattern-dependent soft error rate computation technique based on cell library characterization for combinational circuits and sequential circuits. We develop a dynamic soft error rate simulator. We use benchmark circuits from ISCAS’89 and ITC’99 to compare our proposed technique with HSpice simulation. Our proposed technique is 5 ~ 6 orders of magnitude speed-up over HSpice simulation with less than 3% error. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T04:18:11Z (GMT). No. of bitstreams: 1 ntu-99-R97943068-1.pdf: 2645738 bytes, checksum: e1840ae6f64c2343f6e11be994f7f7ce (MD5) Previous issue date: 2010 | en |
dc.description.tableofcontents | 誌謝 I
摘要 II Abstract III Contents IV Figures VI Tables IX 1. Introduction 1 2. Background 5 2.1. The Definition of Soft Error 5 2.2. Radiation Mechanisms 7 2.3. Sensitive Regions 8 2.4. Transient Fault Model 10 2.5. Masking Mechanisms 12 2.5.1. Logical Masking 12 2.5.2. Electrical Masking 12 2.5.3. Latching-Window Masking 13 3. Proposed Technique 14 3.1. Cell Library Characterization 14 3.1.1. The Standard Cell Library in 45nm Predictive Technology Model 14 3.1.2. Choosing Parameters of Transient Fault Model 15 3.1.3. Look-Up Table Construction for the Standard Cell Library 16 3.2. Fault Generation 24 3.3. Masking Models 28 3.3.1. Logical Masking Model 29 3.3.2. Electrical Masking Model 30 3.3.3. Latching-Window Masking Model 37 3.4. Fault Merging 48 3.5. A Special Case about Fan-Out Reconvergence 56 3.6. Computing the Soft Error Rate 60 4. Discussion 67 5. Experiment Results 73 6. Conclusion 89 7. Reference 90 | |
dc.language.iso | en | |
dc.title | 動態的軟性錯誤率模擬器 | zh_TW |
dc.title | A Dynamic Soft Error Rate Simulator | en |
dc.type | Thesis | |
dc.date.schoolyear | 98-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 李建模,張益興,溫宏斌 | |
dc.subject.keyword | 軟性錯誤,動態, | zh_TW |
dc.subject.keyword | soft error,dynamic, | en |
dc.relation.page | 92 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2010-07-28 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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