請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/20128
標題: | GATK變異尋找工具的硬體加速 Acceleration of Variant Discovery Tool in GATK |
作者: | Zi-Yuan Lin 林子源 |
指導教授: | 陳少傑(Sao-Jie Chen) |
關鍵字: | 基因定序,GATK 基因體分析工具包,DNA變異探索, Genome Sequencing,GATK,DNA Variant Calling, |
出版年 : | 2018 |
學位: | 碩士 |
摘要: | 本論文提出一個針對生物基因定序(DNA Sequencing)之應用軟體GATK (Genome Analysis Tool-Kit)中變異探索(Variant Discovery)步驟流程改良的軟硬體混合設計的加速方式。近年來由於生物醫學的研究與發展、次世代定序(Next Generation Sequencing)技術的發明,使得基因定序技術已有相當大幅度地突破,現今的基因定序之應用軟體以麻省理工Broad Institute 所發展的GATK 基因序列分析工具包較為著名,並在生物及醫學領域的研究中被廣泛使用。然而這類軟體仍存在著許多缺陷,例如執行效能受限於其軟體開發環境、部份功能的演算法效率不佳,以及記憶體使用需求高等問題,因此極需以另一種方式實作GATK 以解決上述問題。
在本論文中我們會以軟體語言(C++)以及硬體描述語言(Verilog HDL)對GATK 中的變異探索流程進行重新設計,其中包含了簡化流程中的演算法並降低運算複雜度、使用平行化的硬體架構達到加速目的;並在硬體描述語言上,透過 Field Programmable Gate Array (FPGA)驗證我們的設計。目前在硬體與軟體模擬已達到相較GATK 軟體約6.2倍的加速與原先相比不到10%的記憶體使用量。 This work presents a digital hardware design to accelerate HaplotypeCaller, a tool in the Variant Discovery phase of Genome Analysis Tool-Kit (GATK) [1], which is a software tools package for genetic sequencing data analyzing. Because of the progress of development in the biomedical field and the appearance of Next Generation Sequencing (NGS) [2] technique, there has been a breakthrough on large DNA sequencing throughput. Many software tools have been developed for DNA sequencing. In this Thesis, we will introduce a tool-kit called GATK, a well-known Java-based command line tool used by many Biomedical Scientists. However, these kinds of tools suffer from the low performance issue caused by their software development environment, and some of the algorithms may not work perfectly under certain special cases. Therefore, a new design using other language and platform is needed for further clinical analysis and research. In our work, we implement the redesign of a tool called HaplotypeCaller, which is the most important tool in the Variant Discovery phase of GATK. The work is done by using a software hardware co-design environment of C++ and Verilog, and implementing the hardware part on FPGA. The overall performance of our software and hardware co-design platform achieved a speed-up of 6.2 times. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/20128 |
DOI: | 10.6342/NTU201800688 |
全文授權: | 未授權 |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-107-1.pdf 目前未授權公開取用 | 3.37 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。