小面積並具快速收斂相關性迴路之次諧波注入頻率合成器

Abstract

這篇論文提出一個小面積並具快速收斂相關性迴路之次諧波注入頻率合成器。相域的分析驗證了一個二階次諧波注入的鎖相迴路能夠穩定，即使迴路濾波器只使用一個小電容。因此，迴路濾波器的面積大量減少而能夠實現一個小面積的次諧波注入鎖相迴路。此外，藉由二元搜尋演算法，實現了一個快速收斂的相關性迴路，在背景校正數位時間轉換器的增益誤差。此演算法確保相關器輸出的初始值能夠接近其最終值，並且不受製程、電源、溫度變異的影響。此晶片以40奈米製程製造，其核心面積為0.0104平方公厘，相關性迴路的收斂時間在30微秒之內，使用1.1伏電源的功率消耗為3.19毫瓦。

In this thesis, an area-efficient subharmonically injection-locked fractional-N frequency synthesizer is proposed. The phase domain analysis confirms that a second-order subharmonically injection-locked phase-locked loop (SIPLL) can be stable even if the loop filter is composed of only a tiny capacitor. Thus, the area of the loop filter shrinks dramatically to realize an area-efficient SIPLL. Besides, a fast-converging correlation loop is used to calibrate the gain error of the digital-to-time converter in background by using a binary search algorithm. It ensures the initial output of the correlator close to the final one and is insensitive to process/supply/temperature variations. The chip is fabricated in a 40 nm process and occupies a core area of 0.0104 mm2. The converging time of the correlation loop is within 30μs. The power consumption is 3.19mW from a 1.1 V supply.