使用校正技巧於電荷泵與頻寬的CMOS寬頻鎖相迴路

Abstract

本論文提出了採用0.18微米和90奈米CMOS互補式金氧半導體製程的低突波寬頻鎖相迴路，電荷泵電流校準技術使得鎖相迴路在寬頻率範圍內保持恆定的迴路頻寬，並實現較低的參考突波。第一級電荷泵電流校準和機制與自動頻帶跳頻控制整合一起，校正迴路頻寬同時確保足夠的負電導提供電壓控制的振盪器在整個頻率範圍內發揮作用。第二級電荷泵電流校準電荷泵電流不匹配與脈衝寬度的縮放技術相結合。CMOS 0.18微米PLL操作在4.7-6.1GHz，參考突波低於68.5分貝，在1MHz偏移情況下相位雜訊為-116dBc/Hz。CMOS 90 奈米PLL操作在39.5-47.1GHz，參考突波低於57.6分貝，在1MHz偏移情況下相位雜訊為-92.35dBc/Hz。

This thesis presents a 0.18-μm and a 90-nm CMOS wideband phase-locked loops with low reference spurs. A charge-pump current calibration technique is proposed to maintain a constant loop bandwidth for wide operation frequency range and achieve low reference spurs. First level charge-pump current calibration is seamlessly incorporated in the automatic frequency band hopping control and the mechanism also ensures enough negative transconductance for the voltage-controlled oscillator to function throughout the whole frequency range. The charge-pump mismatch is calibrated by second level charge-pump current calibration combined with a pulse-width scaling technique. The proposed CMOS 0.18-μm PLL operation frequency range covers from 4.7 GHz to 6.1GHz. The measured phase noise is -116 dBc/Hz at 1MHz offset and the reference spur is -68.5 dBc. The proposed CMOS 90-nm PLL operates form 39.5-47.1GHz. The reference spur is below -57.6dB. The measured phase noise is -92.35dBc/Hz at 1MHz offset.