嵌入式多媒體記憶卡驗證環境實作

Abstract

隨著晶片設計日趨複雜，如何驗證產品功能，確認其表現符合預期，這已變成一項挑戰,對驗證工程師來說，最重要的議題是：如何快速模擬系統同時達到功能性 測試的高含概率。如此一來，使得IC業界可以縮短新產品上市時程，提升產品競爭力。 本論文設計並實作一個階層式，基於物件導向語言SystemVerilog的驗證環境，利用其物件導向的特性，提高程式碼重複使用率，不僅加速驗證程序、也簡化測試程式撰寫的複雜度；利用SystemVerilog中的Constrained- Random Stimulus Generation 功能，在有限的集合中隨機產生測試向量，以提高找到電路錯誤的機率，使驗證更加完整可靠。 嵌入式多媒體記憶卡(Embedded MultiMediaCard) 是一個具有美好前景的規格，有鑒於此，我們設計實作一個具上述優勢的驗證環境，提出一套匯流排功能性模組(Bus Functional Model)，希望幫助設計者更有效去開發產品，進而促進IC設計產業的發展。

As IC design gets more complicated, verification of product functionality is becoming a challenging task to check the consistency between result and expectation. Therefore, to reduce the simulation time and to increase the functional coverage simultaneously are the two big issues for verification engineers. As a result, IC industry can shorten the process schedule of new products before launching in the market. Subsequently it helps to improve the competitiveness of the product. In this thesis, we design and implement a layered verification environment based on object oriented language, SystemVerilog. The object-oriented characteristics and built-in functional coverage mechanism makes this environment more efficient and reliable. Utilizing the Constrained-Random Stimulus Generation property in SystemVerilog, the stimulus is generated randomly in a restricted subset, thus it not only raises the probability of hitting a bug but also makes programming task easier. Embedded MultiMediaCard (eMMC) is a perfect interconnecting interface with prospects. Consequently, we design and implement a verification environment with the advantages as mentioned above in hopes of assisting engineers to develop more efficient product and boosting IC industries.