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DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 郭斯彥 | |
dc.contributor.author | Chung-Hsun Wu | en |
dc.contributor.author | 吳長勳 | zh_TW |
dc.date.accessioned | 2021-06-08T00:13:36Z | - |
dc.date.copyright | 2013-08-08 | |
dc.date.issued | 2013 | |
dc.date.submitted | 2013-08-02 | |
dc.identifier.citation | [1] Embedded MultiMediaCard (eMMC) Electrical standard , version 4.51, JEDEC Solid State Technology Association, June 2011
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Proceedings. 4th International Conference on. IEEE, 2001. [9] IEEE System Verilog Working Group. 'IEEE Standard for SystemVerilog–Unified Hardware Design, Specification, and Verification (IEEE Std 1800-2005).' (2005). [10] Bricaud, Pierre J. 'IP reuse creation for system-on-a-chip design.' Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999. IEEE, 1999. [11] Rich, David I. 'The evolution of SystemVerilog.' IEEE Design & Test of Computers 20.4 (2003): 82-84. [12] Bacchini, Francine, et al. 'Building a verification test plan: trading brute force for finesse.' Design Automation Conference, 2006 43rd ACM/IEEE. IEEE, 2006. [13] Bacchini, Francine, et al. 'Verification Coverage: When is Enough, Enough?.'Design Automation Conference, 2007. DAC'07. 44th ACM/IEEE. IEEE, 2007. [14] Rancea, I., and V. Sgarciu. 'Functional verification of digital circuits using a software system.' Automation, Quality and Testing, Robotics, 2008. AQTR 2008. IEEE International Conference on. Vol. 1. IEEE, 2008. [15] Song, Min-An, Ting-Chun Huang, and Sy-Yen Kuo. 'A functional verification environment for advanced switching architecture.' Electronic Design, Test and Applications, 2006. DELTA 2006. Third IEEE International Workshop on. IEEE, 2006. [16] Chonnad, Shivakumar, and Balachander Needamangalam. 'A layered approach to behavioral modeling of bus protocols.' ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International. IEEE, 2000. [17] Bergeron, Janick, ed. Verification methodology manual for SystemVerilog. Springer, 2006. [18] Morse, Janice M., et al. 'Verification strategies for establishing reliability and validity in qualitative research.' International journal of qualitative methods 1.2 (2008): 13-22. [19] Glasser, Mark. 'Transaction-Level Modeling.' Open Verification Methodology Cookbook. Springer New York, 2009. 49-68. [20] Keaveney, Martin, et al. 'The development of advanced verification environments using system verilog.' Signals and Systems Conference, 208.(ISSC 2008). IET Irish. IET, 2008. [21] Spear, Chris. SystemVerilog for Verification: A Guide to Learning the Testbench Language Features. Springer, 2008. [22] Glasser, Mark. Open verification methodology cookbook. Springer Publishing Company, Incorporated, 2009. [23] Chilai Huang. 2013. [Online]. Available: http://www.avery-design.com [24] Bustan, Doron, and John Havlicek. 'Some complexity results for SystemVerilog assertions.' Computer Aided Verification. Springer Berlin Heidelberg, 2006. [25] Reise, Brian G., and David W. Carpenter. 'Method and apparatus for a multipurpose configurable bus independent simulation bus functional model.' U.S. Patent No. 6,678,625. 13 Jan. 2004. [26] Hoxey, Paul, Clayton McDonald, and David Guinther. 'An introduction to symbolic simulation.' published at http://www. eetimes. com (2005). [27] Rashinkar, Prakash, Peter Paterson, and Leena Singh. System-on-a-chip verification: methodology and techniques. Springer, 2001. [28] Keating, Michael, and Pierre Bricaud, eds. Reuse methodology manual: for system-on-a-chip designs. Springer, 2002. [29] Molina, A., and Oswaldo Cadenas. 'Functional verification: approaches and challenges.' Latin American applied research 37.1 (2007): 65-69. [30] Hung-Po Wang, “Verification and Implementation of Bus Functional Models for USB System”, Master Thesis, Graduate Institute of Electronics Engineering, National Taiwan University, 2009. [31] LoBue, Michael T. 'Surveying today's most popular storage interfaces.'Computer 35.12 (2002): 48-55. [32] Liu, Chien-Nan Jimmy, I. Chen, and Jing-Yang Jou. 'An efficient design-for-verification technique for HDLs.' Proceedings of the 2001 Asia and South Pacific Design Automation Conference. ACM, 2001. [33] Bauer, Matthias, and Wolfgang Ecker. 'Hardware/software co-simulation in a VHDL-based test bench approach.' Proceedings of the 34th annual Design Automation Conference. ACM, 1997. [34] Giddens, L. Grant, and Ronald R. Munoz. 'Method of using testbench tests to avoid task collisions in hardware description language.' U.S. Patent No. 6,701,494. 2 Mar. 2004. [35] Yeh, P-Y., et al. 'Effective design-for-testability techniques for H. 264 all-binary integer motion estimation.' Circuits, Devices & Systems, IET 4.5 (2010): 403-413. [36] Chou, Hong-Zu. 'Innovative Verification and Synthesis Techniques for Achieving High-Quality SoC Designs.' (2010). [37] Chang, Keng-Li “Verification and implementation of bus functional model for MIPI M-PHY with unipro PHY adapter” (2012) [38] Corno, Fulvio, et al. 'Automatic test bench generation for validation of RT-level descriptions: an industrial experience.' Proceedings of the conference on Design, automation and test in Europe. ACM, 2000. [39] Cai, Lukai, and Daniel Gajski. 'Transaction level modeling: an overview.'Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis. ACM, 2003. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17446 | - |
dc.description.abstract | 隨著晶片設計日趨複雜,如何驗證產品功能,確認其表現符合預期,這已變成一項挑戰,對驗證工程師來說,最重要的議題是:如何快速模擬系統同時達到功能性
測試的高含概率。如此一來,使得IC業界可以縮短新產品上市時程,提升產品競爭力。 本論文設計並實作一個階層式,基於物件導向語言SystemVerilog的驗證環境,利用其物件導向的特性,提高程式碼重複使用率,不僅加速驗證程序、也簡化測試程式撰寫的複雜度;利用SystemVerilog中的Constrained- Random Stimulus Generation 功能,在有限的集合中隨機產生測試向量,以提高找到電路錯誤的機率,使驗證更加完整可靠。 嵌入式多媒體記憶卡(Embedded MultiMediaCard) 是一個具有美好前景的規格,有鑒於此,我們設計實作一個具上述優勢的驗證環境,提出一套匯流排功能性模組(Bus Functional Model),希望幫助設計者更有效去開發產品,進而促進IC設計產業的發展。 | zh_TW |
dc.description.abstract | As IC design gets more complicated, verification of product functionality is becoming a challenging task to check the consistency between result and expectation. Therefore, to reduce the simulation time and to increase the functional coverage simultaneously are the two big issues for verification engineers. As a result, IC industry can shorten the process schedule of new products before launching in the market. Subsequently it helps to improve the competitiveness of the product.
In this thesis, we design and implement a layered verification environment based on object oriented language, SystemVerilog. The object-oriented characteristics and built-in functional coverage mechanism makes this environment more efficient and reliable. Utilizing the Constrained-Random Stimulus Generation property in SystemVerilog, the stimulus is generated randomly in a restricted subset, thus it not only raises the probability of hitting a bug but also makes programming task easier. Embedded MultiMediaCard (eMMC) is a perfect interconnecting interface with prospects. Consequently, we design and implement a verification environment with the advantages as mentioned above in hopes of assisting engineers to develop more efficient product and boosting IC industries. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T00:13:36Z (GMT). No. of bitstreams: 1 ntu-102-R00943150-1.pdf: 1389342 bytes, checksum: 5a51147d2abc0a64a6442c094a982f53 (MD5) Previous issue date: 2013 | en |
dc.description.tableofcontents | 國立臺灣大學(碩)博士學位論文 口試委員會審定書 #
誌謝 ii 中文摘要 iii ABSTRACT iV CONTENTS v LIST OF FIGURES vi LIST OF TABLES viii Chapter 1 Introduction 1 1-1 Verification IP 2 1-2 Organization of this Thesis 3 Chapter 2 Verification Process 4 2-1 Traditional Verification Scope 4 2-2 Linear Verification 5 2-3 Coverage-based Verification 5 2-4 Specification feature verification 6 Chapter 3 eMMC Architecture Overview 8 3-1 eMMC Architecture Introduction 8 3-2 Memory Addressing 9 3-3 eMMC Device Overview 10 3-4 Bus Protocol 11 3-5 eMMC Functional Description 16 Chapter 4 eMMC Bus Functional Model 17 4-1 Always_Catch_Cmd_Response Block 17 4-2 Ammc_Cmd_Class Block 19 4-3 Always_Send_Response Block 19 4-4 Device_Process_Cmd Block 20 4-5 Always_Send_Rd_Data Block 21 4-6 Always_Catch_Data Block 24 Chapter 5 eMMC Test Environment 26 5.1 Sequence 27 5.1.1 Seq_Cmd0_Preidle 27 5.1.2 Seq_Block_Rw 29 5.2 Test Cases 30 5.2.1 Test_Cmd0_Preidle 31 5.2.2 Test_Multiple 31 5.2.3 Test_Lock_Unlock 32 5.2.4 Test_Interrupt 33 5.3 eMMC Test Result 36 Chapter 6 Conclusion and Future Work 40 6.1 Conclusion 40 6.2 Future Work 41 REFERENCES 42 | |
dc.language.iso | en | |
dc.title | 嵌入式多媒體記憶卡驗證環境實作 | zh_TW |
dc.title | Verification and Implementation of
Embedded MultiMediaCard | en |
dc.type | Thesis | |
dc.date.schoolyear | 101-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 顏嗣鈞,陳英一(ichen@ntut.edu.tw),雷欽隆,陳俊良(Lchen@mail.ntust.edu.tw) | |
dc.subject.keyword | SystemVerilog,嵌入式多媒體記憶卡,匯流排功能性模組, | zh_TW |
dc.subject.keyword | SystemVerilog,Embedded MultiMediaCard, | en |
dc.relation.page | 45 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2013-08-02 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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