應用於微機電震盪器之開鎖機制低功率數位鎖相迴路

Abstract

本篇論文旨在介紹用於微機電震盪器之開鎖機制低功率數位鎖相迴路的設計與實作。此電路目的在於透過鎖相迴路補償微機電震盪器對溫度所造成的頻率飄移現象，並透過開斷鎖機制，我們可以省下約20%的電路功耗，且預期省下70%的系統功耗。而本電路輸出頻率為72MHz,在不同的溫度情況下，頻率精準度皆在數百ppm誤差範圍內。本論文藉由65-nm與0.18-μm標準互補式金氧半導體製程，實現了三個相關的電路。 第一個實作導入了數位鎖頻迴路以加速鎖定過程。為了節省硬體以及功耗，此鎖頻迴路由數位張弛震盪器，bang-bang相位偵測器，除法器以及二位元增益移位器構成。第二個實作中，為了連續輸出，我們增加了一相位注入機制。而為了節省硬體以及功耗，在第三個鎖相迴路設計中，我們使用一鎖定偵測器與開鎖機制來節省功耗。 在1伏特之供應電壓下(1.2伏特於0.18-μm製程)，三個電路之耗能皆小於1毫瓦特。，其面積皆小於1平方毫米。而其功能性以及表現在量測結果中也被進一步驗證。

This thesis illustrates the design and implementation of low power all-digital phase-locked loop with open loop mechanism for MEMS oscillator. The digital phase-locked loop performs 72MHz output with hundreds ppm level frequency accuracy for a wide temperature range, which is designed to calibrate frequency drift of MEMS oscillator under temperature change. With open loop mechanism, we reduce 20% power consumption of digital phase-locked loop circuit, and estimated save 70% system power. By using a standard TSMC 65-nm and 0.18-μm CMOS process, there are three circuits implemented. Firstly, the digital frequency-locked loop architecture is introduced to accelerate the locking process. The proposed architecture is simply composed of digitally controlled oscillator, bang-bang phase detector, digital divider and binary gain shift logic circuit for reducing the hardware cost and power consumption. Secondly, the phase-injection mechanism is applied to phase-locked loop for continuous output. In order to reduce the power consumption, the proposed lock detector is present in the third digital phase-locked loop design. Operated at a 1-V supply voltage (1.2-V at 0.18-μm CMOS process), the fabricated circuits consume a dc power less than 1 mW. Except the testing circuits and pads, the active areas are all less than 1 mm2. The functions and performance are verified in the measurement result.