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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.advisor | 呂良鴻 | |
dc.contributor.author | Ci Li | en |
dc.contributor.author | 李琦 | zh_TW |
dc.date.accessioned | 2021-06-08T00:09:05Z | - |
dc.date.copyright | 2013-08-14 | |
dc.date.issued | 2013 | |
dc.date.submitted | 2013-08-09 | |
dc.identifier.citation | [1] SiT8003. [Online]. Available: http://www.sitime.com/products/low-power-programmable-oscillators.php
[2] MAX7375. [Online]. Available: http://datasheets.maxim-ic.com/en/ds/MAX7375.pdf [3] DSC1028 [Online]. Available: http://www.discera.com/products/standard-oscillators [4] A. Vilas Boas and A. Olmos, ‘‘A Temperature Compensated Digitally Trimmable On-Chip IC Oscillator with Low Voltage Inhibit Capability,’’ in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), Sep. 2004, vol.1, pp.501—504. [5] Yusuke Tokunaga, Shiro Sakiyama, Akinori Matsumoto and Shiro Dosho, “An On-Chip CMOS Relaxation Oscillator with Voltage Averaging Feedback,” J. Solid-State Circuits, vol. 45, no. 6, pp. 1150-1158, June, 2010. [6] Kunil Choe, Olivier D. Bernal, David Nuttman and Minkyu Je, ‘‘A Precision Relaxation Oscillator with a Self-Clocked Offset-Cancellation Scheme for Implantable Biomedical SoCs,’’ in IEEE Intl. Solid-State Circuits Conf. Dig. Tech. Papers, Feb., 2009, pp. 402-403. [7] C.-M. Hsu, “Techniques for high-performance digital frequency synthesis and phase control, ” PhD Thesis, Massachusetts Institute of Technology, Sep. 2008. [8] V. Kratyuk, P. Kurmar, U.K. Moon, and K. Mayaram,“A Design Procedure for All-Digital Phase-Looked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy,” IEEE Trans. Circuits Syst. II. , vol. 54, no. 3, March 2007. [9] N. Da Dalt., “A Design Oriented Study of the Nonlinear Dynamics of Digital Bang-Bang PLLs,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 1,pp. 21–31, Jan. 2005. [10] N. Da Dalt, E. Thaller, P. Gregorius, and L. Gazsi, “A compact tripleband low-jitter digital LC PLL with programmable coil in 130-nmCMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1482–1490,Jul. 2005 [11] J. [11] Sklansky “Conditional-sum addition logic,” IRE Trans. Electronic Computers, vol. EC-9, June 1960, pp. 226-231. [12] M. Zanuso, D. Tasca, S. Levantino, A. Donadel, C. Samori, and A. L.Lacaita, “Noise analysis and minimization in bang-bang digital PLL,”IEEE Trans. Circuits Syst. I—Reg. Papers, vol. 56, no. 11, pp. 835–839,Nov. 2009 [13] N. Da Dalt, “Linearized analysis of a digital bang-bang PLL and its validity limits applied to jitter transfer and jitter generation,” IEEE Trans.Circuits Syst. I—Reg. Papers, vol. 55, no. 11, pp. 3663–3675, Nov.2008 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17367 | - |
dc.description.abstract | 本篇論文旨在介紹用於微機電震盪器之開鎖機制低功率數位鎖相迴路的設計與實作。此電路目的在於透過鎖相迴路補償微機電震盪器對溫度所造成的頻率飄移現象,並透過開斷鎖機制,我們可以省下約20%的電路功耗,且預期省下70%的系統功耗。而本電路輸出頻率為72MHz,在不同的溫度情況下,頻率精準度皆在數百ppm誤差範圍內。本論文藉由65-nm與0.18-μm標準互補式金氧半導體製程,實現了三個相關的電路。
第一個實作導入了數位鎖頻迴路以加速鎖定過程。為了節省硬體以及功耗,此鎖頻迴路由數位張弛震盪器,bang-bang相位偵測器,除法器以及二位元增益移位器構成。第二個實作中,為了連續輸出,我們增加了一相位注入機制。而為了節省硬體以及功耗,在第三個鎖相迴路設計中,我們使用一鎖定偵測器與開鎖機制來節省功耗。 在1伏特之供應電壓下(1.2伏特於0.18-μm製程),三個電路之耗能皆小於1毫瓦特。,其面積皆小於1平方毫米。而其功能性以及表現在量測結果中也被進一步驗證。 | zh_TW |
dc.description.abstract | This thesis illustrates the design and implementation of low power all-digital phase-locked loop with open loop mechanism for MEMS oscillator. The digital phase-locked loop performs 72MHz output with hundreds ppm level frequency accuracy for a wide temperature range, which is designed to calibrate frequency drift of MEMS oscillator under temperature change. With open loop mechanism, we reduce 20% power consumption of digital phase-locked loop circuit, and estimated save 70% system power. By using a standard TSMC 65-nm and 0.18-μm CMOS process, there are three circuits implemented.
Firstly, the digital frequency-locked loop architecture is introduced to accelerate the locking process. The proposed architecture is simply composed of digitally controlled oscillator, bang-bang phase detector, digital divider and binary gain shift logic circuit for reducing the hardware cost and power consumption. Secondly, the phase-injection mechanism is applied to phase-locked loop for continuous output. In order to reduce the power consumption, the proposed lock detector is present in the third digital phase-locked loop design. Operated at a 1-V supply voltage (1.2-V at 0.18-μm CMOS process), the fabricated circuits consume a dc power less than 1 mW. Except the testing circuits and pads, the active areas are all less than 1 mm2. The functions and performance are verified in the measurement result. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T00:09:05Z (GMT). No. of bitstreams: 1 ntu-102-R00943023-1.pdf: 3890686 bytes, checksum: b62b5136a8131a63842fbe3cac5568e8 (MD5) Previous issue date: 2013 | en |
dc.description.tableofcontents | ABSTRACT VII
TABLE OF CONTENTS IX LIST OF FIGURES XIII LIST OF TABLES XVII CHAPTER1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS OVERVIEW 4 CHAPTER 2 BACKGROUND 7 2.1 INTRODUCTION OF PHASE-LOCKED LOOP 7 2.2 BASIC CONCEPTS OF DIGITAL PHASE-LOCKED LOOP 8 2.3 LINEAR MODEL OF THE ALL-DIGITAL PHASE-LOCKED LOOP 9 2.3.1 Phase-to-Digital Converter 9 2.3.2 Digital Loop Filter 11 2.3.3 Digitally Controlled Oscillator 12 2.3.4 Linear model of system 13 2.4 DESIGN METHODOLOGY 15 CHAPTER 3 A LOW POWER FREQUENCY-LOCKED LOOP WITH OPEN LOOP MECHANISM FOR MEMS OSCILLATOR 17 3.1 INTRODUCTION 17 3.2 THE PROPOSED ALL-DIGITAL FREQUENCY-LOCKED LOOP ARCHITECTURE 21 3.2.1 System Overview 21 3.2.2 Bang-bang Phase Detector 22 3.2.3 Binary Gain Shift Logic Circuit 23 3.2.4 Digitally Controlled Oscillator 24 3.2.5 Output Counter 27 3.3 FREQUENCY ERROR ANALYSIS 28 3.4 EXPERIMENTAL RESULT 30 3.5 CONCLUSION 34 CHAPTER 4 A LOW POWER PHASE-LOCKED LOOP WITH OPEN LOOP MECHANISM FOR MEMS OSCILLATOR 35 4.1 INTRODUCTION 36 4.2 THE PROPOSED ADPLL CIRCUIT ARCHITECTURE 37 4.2.1 Timing Schedule of Proposed ADPLL 38 4.2.2 Frequency-Locked Loop 39 4.2.3 Bang-Bang PLL 40 4.2.4 Output and Loop Control Circuit 41 4.3 EXPERIMENTAL RESULT 45 4.4 CONCLUSION 49 CHAPTER5 A LOW POWER PHASE-LOCKED LOOP WITH OPEN LOOP AND PHASE-ALIGNMENT LOCKING MECHANISM FOR MEMS OSCILLATOR 51 5.1 INTRODUCTION 52 5.2 THE PROPOSED ADPLL CIRCUIT ARCHITECTURE 52 5.2.1 Timing Schedule of Proposed ADPLL 53 5.2.2 Digitally-Controlled Oscillator 54 5.2.3 Output and Loop Control Circuit 55 5.3 SIMULATION RESULT 57 CHAPTER6 CONCLUSION 63 BIBLIOGRAPHY 65 | |
dc.language.iso | en | |
dc.title | 應用於微機電震盪器之開鎖機制低功率數位鎖相迴路 | zh_TW |
dc.title | Low Power All-Digital Phase-Locked Loop with Open loop Mechanism for MEMS Oscillator | en |
dc.type | Thesis | |
dc.date.schoolyear | 101-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 魏駿愷,闕河鳴 | |
dc.subject.keyword | 微機電震盪器,數位鎖相迴路,開鎖機制,低功率,張弛震盪器, | zh_TW |
dc.subject.keyword | Low Power,All-Digital Phase-Locked Loop,Open loop Mechanism,MEMS Oscillator,Relaxation Oscillator, | en |
dc.relation.page | 68 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2013-08-09 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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